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![Rob Herring](/assets/img/avatar_default.png)
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by: Tzung-Bi Shih <tzungbi@kernel.org> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
329 lines
8.4 KiB
C
329 lines
8.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* MediaTek display pulse-width-modulation controller driver.
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* Copyright (c) 2015 MediaTek Inc.
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* Author: YH Huang <yh.huang@mediatek.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/slab.h>
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#define DISP_PWM_EN 0x00
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#define PWM_CLKDIV_SHIFT 16
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#define PWM_CLKDIV_MAX 0x3ff
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#define PWM_CLKDIV_MASK (PWM_CLKDIV_MAX << PWM_CLKDIV_SHIFT)
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#define PWM_PERIOD_BIT_WIDTH 12
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#define PWM_PERIOD_MASK ((1 << PWM_PERIOD_BIT_WIDTH) - 1)
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#define PWM_HIGH_WIDTH_SHIFT 16
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#define PWM_HIGH_WIDTH_MASK (0x1fff << PWM_HIGH_WIDTH_SHIFT)
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struct mtk_pwm_data {
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u32 enable_mask;
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unsigned int con0;
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u32 con0_sel;
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unsigned int con1;
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bool has_commit;
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unsigned int commit;
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unsigned int commit_mask;
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unsigned int bls_debug;
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u32 bls_debug_mask;
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};
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struct mtk_disp_pwm {
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struct pwm_chip chip;
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const struct mtk_pwm_data *data;
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struct clk *clk_main;
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struct clk *clk_mm;
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void __iomem *base;
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bool enabled;
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};
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static inline struct mtk_disp_pwm *to_mtk_disp_pwm(struct pwm_chip *chip)
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{
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return container_of(chip, struct mtk_disp_pwm, chip);
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}
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static void mtk_disp_pwm_update_bits(struct mtk_disp_pwm *mdp, u32 offset,
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u32 mask, u32 data)
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{
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void __iomem *address = mdp->base + offset;
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u32 value;
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value = readl(address);
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value &= ~mask;
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value |= data;
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writel(value, address);
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}
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static int mtk_disp_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
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u32 clk_div, period, high_width, value;
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u64 div, rate;
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int err;
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if (state->polarity != PWM_POLARITY_NORMAL)
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return -EINVAL;
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if (!state->enabled && mdp->enabled) {
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mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN,
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mdp->data->enable_mask, 0x0);
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clk_disable_unprepare(mdp->clk_mm);
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clk_disable_unprepare(mdp->clk_main);
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mdp->enabled = false;
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return 0;
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}
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if (!mdp->enabled) {
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err = clk_prepare_enable(mdp->clk_main);
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if (err < 0) {
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dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n",
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ERR_PTR(err));
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return err;
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}
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err = clk_prepare_enable(mdp->clk_mm);
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if (err < 0) {
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dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n",
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ERR_PTR(err));
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clk_disable_unprepare(mdp->clk_main);
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return err;
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}
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}
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/*
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* Find period, high_width and clk_div to suit duty_ns and period_ns.
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* Calculate proper div value to keep period value in the bound.
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*
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* period_ns = 10^9 * (clk_div + 1) * (period + 1) / PWM_CLK_RATE
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* duty_ns = 10^9 * (clk_div + 1) * high_width / PWM_CLK_RATE
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*
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* period = (PWM_CLK_RATE * period_ns) / (10^9 * (clk_div + 1)) - 1
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* high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1))
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*/
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rate = clk_get_rate(mdp->clk_main);
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clk_div = mul_u64_u64_div_u64(state->period, rate, NSEC_PER_SEC) >>
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PWM_PERIOD_BIT_WIDTH;
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if (clk_div > PWM_CLKDIV_MAX) {
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if (!mdp->enabled) {
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clk_disable_unprepare(mdp->clk_mm);
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clk_disable_unprepare(mdp->clk_main);
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}
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return -EINVAL;
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}
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div = NSEC_PER_SEC * (clk_div + 1);
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period = mul_u64_u64_div_u64(state->period, rate, div);
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if (period > 0)
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period--;
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high_width = mul_u64_u64_div_u64(state->duty_cycle, rate, div);
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value = period | (high_width << PWM_HIGH_WIDTH_SHIFT);
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if (mdp->data->bls_debug && !mdp->data->has_commit) {
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/*
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* For MT2701, disable double buffer before writing register
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* and select manual mode and use PWM_PERIOD/PWM_HIGH_WIDTH.
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*/
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mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug,
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mdp->data->bls_debug_mask,
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mdp->data->bls_debug_mask);
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mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
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mdp->data->con0_sel,
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mdp->data->con0_sel);
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}
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mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
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PWM_CLKDIV_MASK,
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clk_div << PWM_CLKDIV_SHIFT);
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mtk_disp_pwm_update_bits(mdp, mdp->data->con1,
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PWM_PERIOD_MASK | PWM_HIGH_WIDTH_MASK,
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value);
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if (mdp->data->has_commit) {
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mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
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mdp->data->commit_mask,
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mdp->data->commit_mask);
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mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
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mdp->data->commit_mask,
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0x0);
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}
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mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
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mdp->data->enable_mask);
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mdp->enabled = true;
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return 0;
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}
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static int mtk_disp_pwm_get_state(struct pwm_chip *chip,
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struct pwm_device *pwm,
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struct pwm_state *state)
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{
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struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
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u64 rate, period, high_width;
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u32 clk_div, pwm_en, con0, con1;
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int err;
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err = clk_prepare_enable(mdp->clk_main);
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if (err < 0) {
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dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err));
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return err;
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}
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err = clk_prepare_enable(mdp->clk_mm);
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if (err < 0) {
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dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err));
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clk_disable_unprepare(mdp->clk_main);
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return err;
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}
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/*
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* Apply DISP_PWM_DEBUG settings to choose whether to enable or disable
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* registers double buffer and manual commit to working register before
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* performing any read/write operation
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*/
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if (mdp->data->bls_debug)
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mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug,
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mdp->data->bls_debug_mask,
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mdp->data->bls_debug_mask);
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rate = clk_get_rate(mdp->clk_main);
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con0 = readl(mdp->base + mdp->data->con0);
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con1 = readl(mdp->base + mdp->data->con1);
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pwm_en = readl(mdp->base + DISP_PWM_EN);
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state->enabled = !!(pwm_en & mdp->data->enable_mask);
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clk_div = FIELD_GET(PWM_CLKDIV_MASK, con0);
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period = FIELD_GET(PWM_PERIOD_MASK, con1);
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/*
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* period has 12 bits, clk_div 11 and NSEC_PER_SEC has 30,
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* so period * (clk_div + 1) * NSEC_PER_SEC doesn't overflow.
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*/
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state->period = DIV64_U64_ROUND_UP(period * (clk_div + 1) * NSEC_PER_SEC, rate);
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high_width = FIELD_GET(PWM_HIGH_WIDTH_MASK, con1);
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state->duty_cycle = DIV64_U64_ROUND_UP(high_width * (clk_div + 1) * NSEC_PER_SEC,
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rate);
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state->polarity = PWM_POLARITY_NORMAL;
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clk_disable_unprepare(mdp->clk_mm);
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clk_disable_unprepare(mdp->clk_main);
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return 0;
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}
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static const struct pwm_ops mtk_disp_pwm_ops = {
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.apply = mtk_disp_pwm_apply,
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.get_state = mtk_disp_pwm_get_state,
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.owner = THIS_MODULE,
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};
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static int mtk_disp_pwm_probe(struct platform_device *pdev)
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{
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struct mtk_disp_pwm *mdp;
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int ret;
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mdp = devm_kzalloc(&pdev->dev, sizeof(*mdp), GFP_KERNEL);
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if (!mdp)
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return -ENOMEM;
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mdp->data = of_device_get_match_data(&pdev->dev);
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mdp->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(mdp->base))
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return PTR_ERR(mdp->base);
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mdp->clk_main = devm_clk_get(&pdev->dev, "main");
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if (IS_ERR(mdp->clk_main))
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return PTR_ERR(mdp->clk_main);
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mdp->clk_mm = devm_clk_get(&pdev->dev, "mm");
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if (IS_ERR(mdp->clk_mm))
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return PTR_ERR(mdp->clk_mm);
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mdp->chip.dev = &pdev->dev;
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mdp->chip.ops = &mtk_disp_pwm_ops;
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mdp->chip.npwm = 1;
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ret = pwmchip_add(&mdp->chip);
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if (ret < 0) {
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dev_err(&pdev->dev, "pwmchip_add() failed: %pe\n", ERR_PTR(ret));
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return ret;
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}
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platform_set_drvdata(pdev, mdp);
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return 0;
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}
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static void mtk_disp_pwm_remove(struct platform_device *pdev)
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{
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struct mtk_disp_pwm *mdp = platform_get_drvdata(pdev);
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pwmchip_remove(&mdp->chip);
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}
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static const struct mtk_pwm_data mt2701_pwm_data = {
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.enable_mask = BIT(16),
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.con0 = 0xa8,
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.con0_sel = 0x2,
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.con1 = 0xac,
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.has_commit = false,
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.bls_debug = 0xb0,
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.bls_debug_mask = 0x3,
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};
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static const struct mtk_pwm_data mt8173_pwm_data = {
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.enable_mask = BIT(0),
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.con0 = 0x10,
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.con0_sel = 0x0,
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.con1 = 0x14,
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.has_commit = true,
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.commit = 0x8,
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.commit_mask = 0x1,
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};
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static const struct mtk_pwm_data mt8183_pwm_data = {
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.enable_mask = BIT(0),
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.con0 = 0x18,
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.con0_sel = 0x0,
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.con1 = 0x1c,
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.has_commit = false,
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.bls_debug = 0x80,
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.bls_debug_mask = 0x3,
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};
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static const struct of_device_id mtk_disp_pwm_of_match[] = {
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{ .compatible = "mediatek,mt2701-disp-pwm", .data = &mt2701_pwm_data},
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{ .compatible = "mediatek,mt6595-disp-pwm", .data = &mt8173_pwm_data},
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{ .compatible = "mediatek,mt8173-disp-pwm", .data = &mt8173_pwm_data},
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{ .compatible = "mediatek,mt8183-disp-pwm", .data = &mt8183_pwm_data},
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{ }
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};
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MODULE_DEVICE_TABLE(of, mtk_disp_pwm_of_match);
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static struct platform_driver mtk_disp_pwm_driver = {
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.driver = {
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.name = "mediatek-disp-pwm",
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.of_match_table = mtk_disp_pwm_of_match,
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},
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.probe = mtk_disp_pwm_probe,
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.remove_new = mtk_disp_pwm_remove,
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};
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module_platform_driver(mtk_disp_pwm_driver);
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MODULE_AUTHOR("YH Huang <yh.huang@mediatek.com>");
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MODULE_DESCRIPTION("MediaTek SoC display PWM driver");
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MODULE_LICENSE("GPL v2");
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