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![Uwe Kleine-König](/assets/img/avatar_default.png)
Dividing by the result of a division looses precision. Consider for example
clk_rate = 33000000 and period_ns = 500001. Then
clk_rate / (NSEC_PER_SEC / period_ns)
has the exact value 16500.033, but in C this evaluates to 16508. It gets
worse for even bigger values of period_ns, so with period_ns = 500000001,
the exact result is 16500000.033 while in C we get 33000000.
For that reason use
clk_rate * period_ns / NSEC_PER_SEC
instead which doesn't suffer from this problem. To ensure this doesn't
overflow add a safeguard check for clk_rate.
Note that duty > period can never happen, so the respective check can be
dropped.
Incidentally this fixes a division by zero if period_ns > NSEC_PER_SEC.
Another side effect is that values bigger than INT_MAX for period and
duty_cyle are not wrongly discarded any more.
Fixes: 99b82abb0a
("pwm: Add Renesas TPU PWM driver")
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
505 lines
12 KiB
C
505 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* R-Mobile TPU PWM driver
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*
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* Copyright (C) 2012 Renesas Solutions Corp.
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/pwm.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#define TPU_CHANNEL_MAX 4
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#define TPU_TSTR 0x00 /* Timer start register (shared) */
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#define TPU_TCRn 0x00 /* Timer control register */
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#define TPU_TCR_CCLR_NONE (0 << 5)
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#define TPU_TCR_CCLR_TGRA (1 << 5)
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#define TPU_TCR_CCLR_TGRB (2 << 5)
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#define TPU_TCR_CCLR_TGRC (5 << 5)
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#define TPU_TCR_CCLR_TGRD (6 << 5)
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#define TPU_TCR_CKEG_RISING (0 << 3)
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#define TPU_TCR_CKEG_FALLING (1 << 3)
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#define TPU_TCR_CKEG_BOTH (2 << 3)
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#define TPU_TMDRn 0x04 /* Timer mode register */
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#define TPU_TMDR_BFWT (1 << 6)
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#define TPU_TMDR_BFB (1 << 5)
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#define TPU_TMDR_BFA (1 << 4)
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#define TPU_TMDR_MD_NORMAL (0 << 0)
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#define TPU_TMDR_MD_PWM (2 << 0)
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#define TPU_TIORn 0x08 /* Timer I/O control register */
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#define TPU_TIOR_IOA_0 (0 << 0)
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#define TPU_TIOR_IOA_0_CLR (1 << 0)
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#define TPU_TIOR_IOA_0_SET (2 << 0)
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#define TPU_TIOR_IOA_0_TOGGLE (3 << 0)
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#define TPU_TIOR_IOA_1 (4 << 0)
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#define TPU_TIOR_IOA_1_CLR (5 << 0)
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#define TPU_TIOR_IOA_1_SET (6 << 0)
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#define TPU_TIOR_IOA_1_TOGGLE (7 << 0)
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#define TPU_TIERn 0x0c /* Timer interrupt enable register */
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#define TPU_TSRn 0x10 /* Timer status register */
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#define TPU_TCNTn 0x14 /* Timer counter */
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#define TPU_TGRAn 0x18 /* Timer general register A */
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#define TPU_TGRBn 0x1c /* Timer general register B */
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#define TPU_TGRCn 0x20 /* Timer general register C */
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#define TPU_TGRDn 0x24 /* Timer general register D */
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#define TPU_CHANNEL_OFFSET 0x10
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#define TPU_CHANNEL_SIZE 0x40
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enum tpu_pin_state {
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TPU_PIN_INACTIVE, /* Pin is driven inactive */
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TPU_PIN_PWM, /* Pin is driven by PWM */
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TPU_PIN_ACTIVE, /* Pin is driven active */
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};
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struct tpu_device;
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struct tpu_pwm_device {
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bool timer_on; /* Whether the timer is running */
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struct tpu_device *tpu;
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unsigned int channel; /* Channel number in the TPU */
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enum pwm_polarity polarity;
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unsigned int prescaler;
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u16 period;
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u16 duty;
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};
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struct tpu_device {
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struct platform_device *pdev;
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struct pwm_chip chip;
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spinlock_t lock;
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void __iomem *base;
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struct clk *clk;
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};
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#define to_tpu_device(c) container_of(c, struct tpu_device, chip)
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static void tpu_pwm_write(struct tpu_pwm_device *tpd, int reg_nr, u16 value)
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{
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void __iomem *base = tpd->tpu->base + TPU_CHANNEL_OFFSET
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+ tpd->channel * TPU_CHANNEL_SIZE;
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iowrite16(value, base + reg_nr);
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}
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static void tpu_pwm_set_pin(struct tpu_pwm_device *tpd,
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enum tpu_pin_state state)
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{
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static const char * const states[] = { "inactive", "PWM", "active" };
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dev_dbg(&tpd->tpu->pdev->dev, "%u: configuring pin as %s\n",
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tpd->channel, states[state]);
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switch (state) {
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case TPU_PIN_INACTIVE:
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tpu_pwm_write(tpd, TPU_TIORn,
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tpd->polarity == PWM_POLARITY_INVERSED ?
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TPU_TIOR_IOA_1 : TPU_TIOR_IOA_0);
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break;
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case TPU_PIN_PWM:
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tpu_pwm_write(tpd, TPU_TIORn,
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tpd->polarity == PWM_POLARITY_INVERSED ?
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TPU_TIOR_IOA_0_SET : TPU_TIOR_IOA_1_CLR);
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break;
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case TPU_PIN_ACTIVE:
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tpu_pwm_write(tpd, TPU_TIORn,
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tpd->polarity == PWM_POLARITY_INVERSED ?
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TPU_TIOR_IOA_0 : TPU_TIOR_IOA_1);
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break;
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}
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}
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static void tpu_pwm_start_stop(struct tpu_pwm_device *tpd, int start)
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{
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unsigned long flags;
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u16 value;
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spin_lock_irqsave(&tpd->tpu->lock, flags);
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value = ioread16(tpd->tpu->base + TPU_TSTR);
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if (start)
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value |= 1 << tpd->channel;
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else
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value &= ~(1 << tpd->channel);
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iowrite16(value, tpd->tpu->base + TPU_TSTR);
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spin_unlock_irqrestore(&tpd->tpu->lock, flags);
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}
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static int tpu_pwm_timer_start(struct tpu_pwm_device *tpd)
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{
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int ret;
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if (!tpd->timer_on) {
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/* Wake up device and enable clock. */
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pm_runtime_get_sync(&tpd->tpu->pdev->dev);
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ret = clk_prepare_enable(tpd->tpu->clk);
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if (ret) {
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dev_err(&tpd->tpu->pdev->dev, "cannot enable clock\n");
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return ret;
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}
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tpd->timer_on = true;
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}
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/*
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* Make sure the channel is stopped, as we need to reconfigure it
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* completely. First drive the pin to the inactive state to avoid
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* glitches.
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*/
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tpu_pwm_set_pin(tpd, TPU_PIN_INACTIVE);
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tpu_pwm_start_stop(tpd, false);
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/*
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* - Clear TCNT on TGRB match
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* - Count on rising edge
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* - Set prescaler
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* - Output 0 until TGRA, output 1 until TGRB (active low polarity)
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* - Output 1 until TGRA, output 0 until TGRB (active high polarity
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* - PWM mode
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*/
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tpu_pwm_write(tpd, TPU_TCRn, TPU_TCR_CCLR_TGRB | TPU_TCR_CKEG_RISING |
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tpd->prescaler);
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tpu_pwm_write(tpd, TPU_TMDRn, TPU_TMDR_MD_PWM);
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tpu_pwm_set_pin(tpd, TPU_PIN_PWM);
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tpu_pwm_write(tpd, TPU_TGRAn, tpd->duty);
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tpu_pwm_write(tpd, TPU_TGRBn, tpd->period);
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dev_dbg(&tpd->tpu->pdev->dev, "%u: TGRA 0x%04x TGRB 0x%04x\n",
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tpd->channel, tpd->duty, tpd->period);
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/* Start the channel. */
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tpu_pwm_start_stop(tpd, true);
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return 0;
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}
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static void tpu_pwm_timer_stop(struct tpu_pwm_device *tpd)
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{
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if (!tpd->timer_on)
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return;
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/* Disable channel. */
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tpu_pwm_start_stop(tpd, false);
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/* Stop clock and mark device as idle. */
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clk_disable_unprepare(tpd->tpu->clk);
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pm_runtime_put(&tpd->tpu->pdev->dev);
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tpd->timer_on = false;
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}
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/* -----------------------------------------------------------------------------
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* PWM API
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*/
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static int tpu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct tpu_device *tpu = to_tpu_device(chip);
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struct tpu_pwm_device *tpd;
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if (pwm->hwpwm >= TPU_CHANNEL_MAX)
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return -EINVAL;
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tpd = kzalloc(sizeof(*tpd), GFP_KERNEL);
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if (tpd == NULL)
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return -ENOMEM;
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tpd->tpu = tpu;
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tpd->channel = pwm->hwpwm;
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tpd->polarity = PWM_POLARITY_NORMAL;
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tpd->prescaler = 0;
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tpd->period = 0;
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tpd->duty = 0;
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tpd->timer_on = false;
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pwm_set_chip_data(pwm, tpd);
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return 0;
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}
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static void tpu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);
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tpu_pwm_timer_stop(tpd);
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kfree(tpd);
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}
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static int tpu_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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u64 duty_ns, u64 period_ns, bool enabled)
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{
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struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);
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struct tpu_device *tpu = to_tpu_device(chip);
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unsigned int prescaler;
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bool duty_only = false;
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u32 clk_rate;
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u64 period;
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u32 duty;
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int ret;
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clk_rate = clk_get_rate(tpu->clk);
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if (unlikely(clk_rate > NSEC_PER_SEC)) {
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/*
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* This won't happen in the nearer future, so this is only a
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* safeguard to prevent the following calculation from
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* overflowing. With this clk_rate * period_ns / NSEC_PER_SEC is
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* not greater than period_ns and so fits into an u64.
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*/
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return -EINVAL;
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}
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period = mul_u64_u64_div_u64(clk_rate, period_ns, NSEC_PER_SEC);
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/*
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* Find the minimal prescaler in [0..3] such that
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*
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* period >> (2 * prescaler) < 0x10000
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*
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* This could be calculated using something like:
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*
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* prescaler = max(ilog2(period) / 2, 7) - 7;
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*
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* but given there are only four allowed results and that ilog2 isn't
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* cheap on all platforms using a switch statement is more effective.
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*/
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switch (period) {
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case 1 ... 0xffff:
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prescaler = 0;
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break;
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case 0x10000 ... 0x3ffff:
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prescaler = 1;
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break;
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case 0x40000 ... 0xfffff:
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prescaler = 2;
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break;
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case 0x100000 ... 0x3fffff:
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prescaler = 3;
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break;
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default:
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return -EINVAL;
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}
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period >>= 2 * prescaler;
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if (duty_ns)
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duty = mul_u64_u64_div_u64(clk_rate, duty_ns,
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(u64)NSEC_PER_SEC << (2 * prescaler));
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else
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duty = 0;
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dev_dbg(&tpu->pdev->dev,
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"rate %u, prescaler %u, period %u, duty %u\n",
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clk_rate, 1 << (2 * prescaler), (u32)period, duty);
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if (tpd->prescaler == prescaler && tpd->period == period)
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duty_only = true;
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tpd->prescaler = prescaler;
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tpd->period = period;
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tpd->duty = duty;
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/* If the channel is disabled we're done. */
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if (!enabled)
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return 0;
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if (duty_only && tpd->timer_on) {
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/*
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* If only the duty cycle changed and the timer is already
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* running, there's no need to reconfigure it completely, Just
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* modify the duty cycle.
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*/
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tpu_pwm_write(tpd, TPU_TGRAn, tpd->duty);
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dev_dbg(&tpu->pdev->dev, "%u: TGRA 0x%04x\n", tpd->channel,
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tpd->duty);
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} else {
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/* Otherwise perform a full reconfiguration. */
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ret = tpu_pwm_timer_start(tpd);
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if (ret < 0)
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return ret;
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}
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if (duty == 0 || duty == period) {
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/*
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* To avoid running the timer when not strictly required, handle
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* 0% and 100% duty cycles as fixed levels and stop the timer.
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*/
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tpu_pwm_set_pin(tpd, duty ? TPU_PIN_ACTIVE : TPU_PIN_INACTIVE);
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tpu_pwm_timer_stop(tpd);
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}
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return 0;
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}
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static int tpu_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
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enum pwm_polarity polarity)
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{
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struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);
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tpd->polarity = polarity;
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return 0;
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}
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static int tpu_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);
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int ret;
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ret = tpu_pwm_timer_start(tpd);
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if (ret < 0)
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return ret;
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/*
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* To avoid running the timer when not strictly required, handle 0% and
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* 100% duty cycles as fixed levels and stop the timer.
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*/
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if (tpd->duty == 0 || tpd->duty == tpd->period) {
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tpu_pwm_set_pin(tpd, tpd->duty ?
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TPU_PIN_ACTIVE : TPU_PIN_INACTIVE);
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tpu_pwm_timer_stop(tpd);
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}
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return 0;
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}
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static void tpu_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);
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/* The timer must be running to modify the pin output configuration. */
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tpu_pwm_timer_start(tpd);
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tpu_pwm_set_pin(tpd, TPU_PIN_INACTIVE);
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tpu_pwm_timer_stop(tpd);
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}
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static int tpu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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int err;
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bool enabled = pwm->state.enabled;
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if (state->polarity != pwm->state.polarity) {
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if (enabled) {
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tpu_pwm_disable(chip, pwm);
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enabled = false;
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}
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err = tpu_pwm_set_polarity(chip, pwm, state->polarity);
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if (err)
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return err;
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}
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if (!state->enabled) {
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if (enabled)
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tpu_pwm_disable(chip, pwm);
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return 0;
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}
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err = tpu_pwm_config(pwm->chip, pwm,
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state->duty_cycle, state->period, enabled);
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if (err)
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return err;
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if (!enabled)
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err = tpu_pwm_enable(chip, pwm);
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return err;
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}
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static const struct pwm_ops tpu_pwm_ops = {
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.request = tpu_pwm_request,
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.free = tpu_pwm_free,
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.apply = tpu_pwm_apply,
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.owner = THIS_MODULE,
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};
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/* -----------------------------------------------------------------------------
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* Probe and remove
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*/
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static int tpu_probe(struct platform_device *pdev)
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{
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struct tpu_device *tpu;
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int ret;
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tpu = devm_kzalloc(&pdev->dev, sizeof(*tpu), GFP_KERNEL);
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if (tpu == NULL)
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return -ENOMEM;
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spin_lock_init(&tpu->lock);
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tpu->pdev = pdev;
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/* Map memory, get clock and pin control. */
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tpu->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(tpu->base))
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return PTR_ERR(tpu->base);
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tpu->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(tpu->clk))
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return dev_err_probe(&pdev->dev, PTR_ERR(tpu->clk), "Failed to get clock\n");
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/* Initialize and register the device. */
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platform_set_drvdata(pdev, tpu);
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tpu->chip.dev = &pdev->dev;
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tpu->chip.ops = &tpu_pwm_ops;
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tpu->chip.npwm = TPU_CHANNEL_MAX;
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ret = devm_pm_runtime_enable(&pdev->dev);
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if (ret < 0)
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return dev_err_probe(&pdev->dev, ret, "Failed to enable runtime PM\n");
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ret = devm_pwmchip_add(&pdev->dev, &tpu->chip);
|
|
if (ret < 0)
|
|
return dev_err_probe(&pdev->dev, ret, "Failed to register PWM chip\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_OF
|
|
static const struct of_device_id tpu_of_table[] = {
|
|
{ .compatible = "renesas,tpu-r8a73a4", },
|
|
{ .compatible = "renesas,tpu-r8a7740", },
|
|
{ .compatible = "renesas,tpu-r8a7790", },
|
|
{ .compatible = "renesas,tpu", },
|
|
{ },
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, tpu_of_table);
|
|
#endif
|
|
|
|
static struct platform_driver tpu_driver = {
|
|
.probe = tpu_probe,
|
|
.driver = {
|
|
.name = "renesas-tpu-pwm",
|
|
.of_match_table = of_match_ptr(tpu_of_table),
|
|
}
|
|
};
|
|
|
|
module_platform_driver(tpu_driver);
|
|
|
|
MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
|
|
MODULE_DESCRIPTION("Renesas TPU PWM Driver");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_ALIAS("platform:renesas-tpu-pwm");
|