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![Rob Herring](/assets/img/avatar_default.png)
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by: Tzung-Bi Shih <tzungbi@kernel.org> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
177 lines
4.8 KiB
C
177 lines
4.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Toshiba Visconti pulse-width-modulation controller driver
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*
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* Copyright (c) 2020 - 2021 TOSHIBA CORPORATION
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* Copyright (c) 2020 - 2021 Toshiba Electronic Devices & Storage Corporation
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*
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* Authors: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
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*
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* Limitations:
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* - The fixed input clock is running at 1 MHz and is divided by either 1,
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* 2, 4 or 8.
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* - When the settings of the PWM are modified, the new values are shadowed
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* in hardware until the PIPGM_PCSR register is written and the currently
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* running period is completed. This way the hardware switches atomically
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* from the old setting to the new.
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* - Disabling the hardware completes the currently running period and keeps
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* the output at low level at all times.
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*/
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#define PIPGM_PCSR(ch) (0x400 + 4 * (ch))
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#define PIPGM_PDUT(ch) (0x420 + 4 * (ch))
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#define PIPGM_PWMC(ch) (0x440 + 4 * (ch))
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#define PIPGM_PWMC_PWMACT BIT(5)
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#define PIPGM_PWMC_CLK_MASK GENMASK(1, 0)
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#define PIPGM_PWMC_POLARITY_MASK GENMASK(5, 5)
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struct visconti_pwm_chip {
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struct pwm_chip chip;
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void __iomem *base;
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};
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static inline struct visconti_pwm_chip *visconti_pwm_from_chip(struct pwm_chip *chip)
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{
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return container_of(chip, struct visconti_pwm_chip, chip);
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}
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static int visconti_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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struct visconti_pwm_chip *priv = visconti_pwm_from_chip(chip);
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u32 period, duty_cycle, pwmc0;
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if (!state->enabled) {
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writel(0, priv->base + PIPGM_PCSR(pwm->hwpwm));
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return 0;
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}
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/*
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* The biggest period the hardware can provide is
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* (0xffff << 3) * 1000 ns
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* This value fits easily in an u32, so simplify the maths by
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* capping the values to 32 bit integers.
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*/
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if (state->period > (0xffff << 3) * 1000)
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period = (0xffff << 3) * 1000;
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else
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period = state->period;
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if (state->duty_cycle > period)
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duty_cycle = period;
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else
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duty_cycle = state->duty_cycle;
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/*
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* The input clock runs fixed at 1 MHz, so we have only
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* microsecond resolution and so can divide by
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* NSEC_PER_SEC / CLKFREQ = 1000 without losing precision.
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*/
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period /= 1000;
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duty_cycle /= 1000;
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if (!period)
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return -ERANGE;
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/*
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* PWMC controls a divider that divides the input clk by a power of two
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* between 1 and 8. As a smaller divider yields higher precision, pick
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* the smallest possible one. As period is at most 0xffff << 3, pwmc0 is
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* in the intended range [0..3].
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*/
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pwmc0 = fls(period >> 16);
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if (WARN_ON(pwmc0 > 3))
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return -EINVAL;
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period >>= pwmc0;
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duty_cycle >>= pwmc0;
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if (state->polarity == PWM_POLARITY_INVERSED)
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pwmc0 |= PIPGM_PWMC_PWMACT;
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writel(pwmc0, priv->base + PIPGM_PWMC(pwm->hwpwm));
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writel(duty_cycle, priv->base + PIPGM_PDUT(pwm->hwpwm));
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writel(period, priv->base + PIPGM_PCSR(pwm->hwpwm));
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return 0;
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}
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static int visconti_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
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struct pwm_state *state)
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{
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struct visconti_pwm_chip *priv = visconti_pwm_from_chip(chip);
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u32 period, duty, pwmc0, pwmc0_clk;
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period = readl(priv->base + PIPGM_PCSR(pwm->hwpwm));
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duty = readl(priv->base + PIPGM_PDUT(pwm->hwpwm));
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pwmc0 = readl(priv->base + PIPGM_PWMC(pwm->hwpwm));
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pwmc0_clk = pwmc0 & PIPGM_PWMC_CLK_MASK;
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state->period = (period << pwmc0_clk) * NSEC_PER_USEC;
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state->duty_cycle = (duty << pwmc0_clk) * NSEC_PER_USEC;
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if (pwmc0 & PIPGM_PWMC_POLARITY_MASK)
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state->polarity = PWM_POLARITY_INVERSED;
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else
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state->polarity = PWM_POLARITY_NORMAL;
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state->enabled = true;
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return 0;
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}
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static const struct pwm_ops visconti_pwm_ops = {
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.apply = visconti_pwm_apply,
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.get_state = visconti_pwm_get_state,
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.owner = THIS_MODULE,
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};
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static int visconti_pwm_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct visconti_pwm_chip *priv;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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priv->chip.dev = dev;
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priv->chip.ops = &visconti_pwm_ops;
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priv->chip.npwm = 4;
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ret = devm_pwmchip_add(&pdev->dev, &priv->chip);
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if (ret < 0)
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return dev_err_probe(&pdev->dev, ret, "Cannot register visconti PWM\n");
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return 0;
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}
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static const struct of_device_id visconti_pwm_of_match[] = {
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{ .compatible = "toshiba,visconti-pwm", },
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{ }
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};
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MODULE_DEVICE_TABLE(of, visconti_pwm_of_match);
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static struct platform_driver visconti_pwm_driver = {
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.driver = {
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.name = "pwm-visconti",
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.of_match_table = visconti_pwm_of_match,
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},
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.probe = visconti_pwm_probe,
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};
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module_platform_driver(visconti_pwm_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>");
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MODULE_ALIAS("platform:pwm-visconti");
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