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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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![Rob Herring](/assets/img/avatar_default.png)
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it was merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Reviewed-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230726233302.3812749-1-robh@kernel.org Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
420 lines
9.8 KiB
C
420 lines
9.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2019 NXP.
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*/
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/reboot.h>
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#include <linux/watchdog.h>
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#define WDOG_CS 0x0
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#define WDOG_CS_FLG BIT(14)
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#define WDOG_CS_CMD32EN BIT(13)
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#define WDOG_CS_PRES BIT(12)
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#define WDOG_CS_ULK BIT(11)
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#define WDOG_CS_RCS BIT(10)
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#define LPO_CLK 0x1
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#define LPO_CLK_SHIFT 8
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#define WDOG_CS_CLK (LPO_CLK << LPO_CLK_SHIFT)
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#define WDOG_CS_EN BIT(7)
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#define WDOG_CS_UPDATE BIT(5)
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#define WDOG_CS_WAIT BIT(1)
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#define WDOG_CS_STOP BIT(0)
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#define WDOG_CNT 0x4
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#define WDOG_TOVAL 0x8
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#define REFRESH_SEQ0 0xA602
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#define REFRESH_SEQ1 0xB480
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#define REFRESH ((REFRESH_SEQ1 << 16) | REFRESH_SEQ0)
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#define UNLOCK_SEQ0 0xC520
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#define UNLOCK_SEQ1 0xD928
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#define UNLOCK ((UNLOCK_SEQ1 << 16) | UNLOCK_SEQ0)
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#define DEFAULT_TIMEOUT 60
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#define MAX_TIMEOUT 128
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#define WDOG_CLOCK_RATE 1000
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#define WDOG_ULK_WAIT_TIMEOUT 1000
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#define WDOG_RCS_WAIT_TIMEOUT 10000
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#define WDOG_RCS_POST_WAIT 3000
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#define RETRY_MAX 5
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static bool nowayout = WATCHDOG_NOWAYOUT;
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module_param(nowayout, bool, 0000);
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MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
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__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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struct imx_wdt_hw_feature {
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bool prescaler_enable;
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u32 wdog_clock_rate;
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};
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struct imx7ulp_wdt_device {
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struct watchdog_device wdd;
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void __iomem *base;
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struct clk *clk;
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bool post_rcs_wait;
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const struct imx_wdt_hw_feature *hw;
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};
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static int imx7ulp_wdt_wait_ulk(void __iomem *base)
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{
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u32 val = readl(base + WDOG_CS);
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if (!(val & WDOG_CS_ULK) &&
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readl_poll_timeout_atomic(base + WDOG_CS, val,
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val & WDOG_CS_ULK, 0,
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WDOG_ULK_WAIT_TIMEOUT))
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return -ETIMEDOUT;
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return 0;
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}
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static int imx7ulp_wdt_wait_rcs(struct imx7ulp_wdt_device *wdt)
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{
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int ret = 0;
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u32 val = readl(wdt->base + WDOG_CS);
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u64 timeout = (val & WDOG_CS_PRES) ?
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WDOG_RCS_WAIT_TIMEOUT * 256 : WDOG_RCS_WAIT_TIMEOUT;
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unsigned long wait_min = (val & WDOG_CS_PRES) ?
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WDOG_RCS_POST_WAIT * 256 : WDOG_RCS_POST_WAIT;
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if (!(val & WDOG_CS_RCS) &&
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readl_poll_timeout(wdt->base + WDOG_CS, val, val & WDOG_CS_RCS, 100,
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timeout))
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ret = -ETIMEDOUT;
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/* Wait 2.5 clocks after RCS done */
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if (wdt->post_rcs_wait)
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usleep_range(wait_min, wait_min + 2000);
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return ret;
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}
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static int _imx7ulp_wdt_enable(struct imx7ulp_wdt_device *wdt, bool enable)
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{
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u32 val = readl(wdt->base + WDOG_CS);
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int ret;
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local_irq_disable();
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writel(UNLOCK, wdt->base + WDOG_CNT);
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ret = imx7ulp_wdt_wait_ulk(wdt->base);
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if (ret)
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goto enable_out;
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if (enable)
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writel(val | WDOG_CS_EN, wdt->base + WDOG_CS);
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else
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writel(val & ~WDOG_CS_EN, wdt->base + WDOG_CS);
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local_irq_enable();
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ret = imx7ulp_wdt_wait_rcs(wdt);
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return ret;
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enable_out:
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local_irq_enable();
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return ret;
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}
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static int imx7ulp_wdt_enable(struct watchdog_device *wdog, bool enable)
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{
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struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);
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int ret;
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u32 val;
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u32 loop = RETRY_MAX;
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do {
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ret = _imx7ulp_wdt_enable(wdt, enable);
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val = readl(wdt->base + WDOG_CS);
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} while (--loop > 0 && ((!!(val & WDOG_CS_EN)) != enable || ret));
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if (loop == 0)
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return -EBUSY;
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return ret;
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}
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static int imx7ulp_wdt_ping(struct watchdog_device *wdog)
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{
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struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);
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writel(REFRESH, wdt->base + WDOG_CNT);
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return 0;
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}
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static int imx7ulp_wdt_start(struct watchdog_device *wdog)
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{
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return imx7ulp_wdt_enable(wdog, true);
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}
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static int imx7ulp_wdt_stop(struct watchdog_device *wdog)
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{
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return imx7ulp_wdt_enable(wdog, false);
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}
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static int _imx7ulp_wdt_set_timeout(struct imx7ulp_wdt_device *wdt,
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unsigned int toval)
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{
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int ret;
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local_irq_disable();
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writel(UNLOCK, wdt->base + WDOG_CNT);
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ret = imx7ulp_wdt_wait_ulk(wdt->base);
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if (ret)
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goto timeout_out;
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writel(toval, wdt->base + WDOG_TOVAL);
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local_irq_enable();
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ret = imx7ulp_wdt_wait_rcs(wdt);
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return ret;
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timeout_out:
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local_irq_enable();
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return ret;
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}
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static int imx7ulp_wdt_set_timeout(struct watchdog_device *wdog,
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unsigned int timeout)
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{
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struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);
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u32 toval = wdt->hw->wdog_clock_rate * timeout;
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u32 val;
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int ret;
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u32 loop = RETRY_MAX;
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do {
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ret = _imx7ulp_wdt_set_timeout(wdt, toval);
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val = readl(wdt->base + WDOG_TOVAL);
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} while (--loop > 0 && (val != toval || ret));
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if (loop == 0)
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return -EBUSY;
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wdog->timeout = timeout;
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return ret;
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}
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static int imx7ulp_wdt_restart(struct watchdog_device *wdog,
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unsigned long action, void *data)
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{
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struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);
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int ret;
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ret = imx7ulp_wdt_enable(wdog, true);
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if (ret)
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return ret;
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ret = imx7ulp_wdt_set_timeout(&wdt->wdd, 1);
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if (ret)
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return ret;
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/* wait for wdog to fire */
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while (true)
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;
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return NOTIFY_DONE;
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}
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static const struct watchdog_ops imx7ulp_wdt_ops = {
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.owner = THIS_MODULE,
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.start = imx7ulp_wdt_start,
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.stop = imx7ulp_wdt_stop,
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.ping = imx7ulp_wdt_ping,
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.set_timeout = imx7ulp_wdt_set_timeout,
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.restart = imx7ulp_wdt_restart,
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};
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static const struct watchdog_info imx7ulp_wdt_info = {
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.identity = "i.MX7ULP watchdog timer",
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.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
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WDIOF_MAGICCLOSE,
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};
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static int _imx7ulp_wdt_init(struct imx7ulp_wdt_device *wdt, unsigned int timeout, unsigned int cs)
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{
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u32 val;
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int ret;
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local_irq_disable();
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val = readl(wdt->base + WDOG_CS);
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if (val & WDOG_CS_CMD32EN) {
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writel(UNLOCK, wdt->base + WDOG_CNT);
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} else {
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mb();
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/* unlock the wdog for reconfiguration */
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writel_relaxed(UNLOCK_SEQ0, wdt->base + WDOG_CNT);
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writel_relaxed(UNLOCK_SEQ1, wdt->base + WDOG_CNT);
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mb();
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}
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ret = imx7ulp_wdt_wait_ulk(wdt->base);
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if (ret)
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goto init_out;
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/* set an initial timeout value in TOVAL */
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writel(timeout, wdt->base + WDOG_TOVAL);
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writel(cs, wdt->base + WDOG_CS);
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local_irq_enable();
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ret = imx7ulp_wdt_wait_rcs(wdt);
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return ret;
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init_out:
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local_irq_enable();
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return ret;
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}
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static int imx7ulp_wdt_init(struct imx7ulp_wdt_device *wdt, unsigned int timeout)
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{
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/* enable 32bit command sequence and reconfigure */
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u32 val = WDOG_CS_CMD32EN | WDOG_CS_CLK | WDOG_CS_UPDATE |
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WDOG_CS_WAIT | WDOG_CS_STOP;
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u32 cs, toval;
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int ret;
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u32 loop = RETRY_MAX;
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if (wdt->hw->prescaler_enable)
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val |= WDOG_CS_PRES;
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do {
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ret = _imx7ulp_wdt_init(wdt, timeout, val);
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toval = readl(wdt->base + WDOG_TOVAL);
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cs = readl(wdt->base + WDOG_CS);
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cs &= ~(WDOG_CS_FLG | WDOG_CS_ULK | WDOG_CS_RCS);
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} while (--loop > 0 && (cs != val || toval != timeout || ret));
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if (loop == 0)
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return -EBUSY;
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return ret;
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}
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static int imx7ulp_wdt_probe(struct platform_device *pdev)
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{
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struct imx7ulp_wdt_device *imx7ulp_wdt;
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struct device *dev = &pdev->dev;
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struct watchdog_device *wdog;
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int ret;
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imx7ulp_wdt = devm_kzalloc(dev, sizeof(*imx7ulp_wdt), GFP_KERNEL);
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if (!imx7ulp_wdt)
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return -ENOMEM;
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platform_set_drvdata(pdev, imx7ulp_wdt);
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imx7ulp_wdt->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(imx7ulp_wdt->base))
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return PTR_ERR(imx7ulp_wdt->base);
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imx7ulp_wdt->clk = devm_clk_get_enabled(dev, NULL);
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if (IS_ERR(imx7ulp_wdt->clk)) {
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dev_err(dev, "Failed to get watchdog clock\n");
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return PTR_ERR(imx7ulp_wdt->clk);
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}
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imx7ulp_wdt->post_rcs_wait = true;
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if (of_device_is_compatible(dev->of_node,
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"fsl,imx8ulp-wdt")) {
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dev_info(dev, "imx8ulp wdt probe\n");
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imx7ulp_wdt->post_rcs_wait = false;
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} else {
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dev_info(dev, "imx7ulp wdt probe\n");
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}
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wdog = &imx7ulp_wdt->wdd;
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wdog->info = &imx7ulp_wdt_info;
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wdog->ops = &imx7ulp_wdt_ops;
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wdog->min_timeout = 1;
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wdog->max_timeout = MAX_TIMEOUT;
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wdog->parent = dev;
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wdog->timeout = DEFAULT_TIMEOUT;
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watchdog_init_timeout(wdog, 0, dev);
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watchdog_stop_on_reboot(wdog);
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watchdog_stop_on_unregister(wdog);
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watchdog_set_drvdata(wdog, imx7ulp_wdt);
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imx7ulp_wdt->hw = of_device_get_match_data(dev);
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ret = imx7ulp_wdt_init(imx7ulp_wdt, wdog->timeout * imx7ulp_wdt->hw->wdog_clock_rate);
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if (ret)
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return ret;
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return devm_watchdog_register_device(dev, wdog);
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}
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static int __maybe_unused imx7ulp_wdt_suspend_noirq(struct device *dev)
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{
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struct imx7ulp_wdt_device *imx7ulp_wdt = dev_get_drvdata(dev);
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if (watchdog_active(&imx7ulp_wdt->wdd))
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imx7ulp_wdt_stop(&imx7ulp_wdt->wdd);
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clk_disable_unprepare(imx7ulp_wdt->clk);
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return 0;
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}
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static int __maybe_unused imx7ulp_wdt_resume_noirq(struct device *dev)
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{
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struct imx7ulp_wdt_device *imx7ulp_wdt = dev_get_drvdata(dev);
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u32 timeout = imx7ulp_wdt->wdd.timeout * imx7ulp_wdt->hw->wdog_clock_rate;
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int ret;
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ret = clk_prepare_enable(imx7ulp_wdt->clk);
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if (ret)
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return ret;
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if (watchdog_active(&imx7ulp_wdt->wdd)) {
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imx7ulp_wdt_init(imx7ulp_wdt, timeout);
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imx7ulp_wdt_start(&imx7ulp_wdt->wdd);
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imx7ulp_wdt_ping(&imx7ulp_wdt->wdd);
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}
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return 0;
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}
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static const struct dev_pm_ops imx7ulp_wdt_pm_ops = {
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SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx7ulp_wdt_suspend_noirq,
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imx7ulp_wdt_resume_noirq)
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};
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static const struct imx_wdt_hw_feature imx7ulp_wdt_hw = {
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.prescaler_enable = false,
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.wdog_clock_rate = 1000,
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};
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static const struct imx_wdt_hw_feature imx93_wdt_hw = {
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.prescaler_enable = true,
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.wdog_clock_rate = 125,
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};
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static const struct of_device_id imx7ulp_wdt_dt_ids[] = {
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{ .compatible = "fsl,imx8ulp-wdt", .data = &imx7ulp_wdt_hw, },
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{ .compatible = "fsl,imx7ulp-wdt", .data = &imx7ulp_wdt_hw, },
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{ .compatible = "fsl,imx93-wdt", .data = &imx93_wdt_hw, },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, imx7ulp_wdt_dt_ids);
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static struct platform_driver imx7ulp_wdt_driver = {
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.probe = imx7ulp_wdt_probe,
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.driver = {
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.name = "imx7ulp-wdt",
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.pm = &imx7ulp_wdt_pm_ops,
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.of_match_table = imx7ulp_wdt_dt_ids,
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},
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};
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module_platform_driver(imx7ulp_wdt_driver);
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MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>");
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MODULE_DESCRIPTION("Freescale i.MX7ULP watchdog driver");
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MODULE_LICENSE("GPL v2");
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