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![Rob Herring](/assets/img/avatar_default.png)
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it was merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Reviewed-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230726233302.3812749-1-robh@kernel.org Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
334 lines
8.6 KiB
C
334 lines
8.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas RZ/G2L WDT Watchdog Driver
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*
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* Copyright (C) 2021 Renesas Electronics Corporation
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*/
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#include <linux/units.h>
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#include <linux/watchdog.h>
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#define WDTCNT 0x00
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#define WDTSET 0x04
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#define WDTTIM 0x08
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#define WDTINT 0x0C
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#define PECR 0x10
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#define PEEN 0x14
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#define WDTCNT_WDTEN BIT(0)
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#define WDTINT_INTDISP BIT(0)
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#define PEEN_FORCE BIT(0)
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#define WDT_DEFAULT_TIMEOUT 60U
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/* Setting period time register only 12 bit set in WDTSET[31:20] */
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#define WDTSET_COUNTER_MASK (0xFFF00000)
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#define WDTSET_COUNTER_VAL(f) ((f) << 20)
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#define F2CYCLE_NSEC(f) (1000000000 / (f))
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#define RZV2M_A_NSEC 730
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static bool nowayout = WATCHDOG_NOWAYOUT;
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module_param(nowayout, bool, 0);
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MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
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__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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enum rz_wdt_type {
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WDT_RZG2L,
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WDT_RZV2M,
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};
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struct rzg2l_wdt_priv {
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void __iomem *base;
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struct watchdog_device wdev;
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struct reset_control *rstc;
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unsigned long osc_clk_rate;
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unsigned long delay;
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unsigned long minimum_assertion_period;
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struct clk *pclk;
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struct clk *osc_clk;
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enum rz_wdt_type devtype;
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};
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static int rzg2l_wdt_reset(struct rzg2l_wdt_priv *priv)
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{
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int err, status;
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if (priv->devtype == WDT_RZV2M) {
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/* WDT needs TYPE-B reset control */
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err = reset_control_assert(priv->rstc);
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if (err)
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return err;
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ndelay(priv->minimum_assertion_period);
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err = reset_control_deassert(priv->rstc);
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if (err)
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return err;
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err = read_poll_timeout(reset_control_status, status,
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status != 1, 0, 1000, false,
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priv->rstc);
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} else {
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err = reset_control_reset(priv->rstc);
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}
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return err;
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}
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static void rzg2l_wdt_wait_delay(struct rzg2l_wdt_priv *priv)
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{
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/* delay timer when change the setting register */
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ndelay(priv->delay);
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}
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static u32 rzg2l_wdt_get_cycle_usec(unsigned long cycle, u32 wdttime)
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{
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u64 timer_cycle_us = 1024 * 1024ULL * (wdttime + 1) * MICRO;
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return div64_ul(timer_cycle_us, cycle);
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}
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static void rzg2l_wdt_write(struct rzg2l_wdt_priv *priv, u32 val, unsigned int reg)
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{
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if (reg == WDTSET)
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val &= WDTSET_COUNTER_MASK;
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writel_relaxed(val, priv->base + reg);
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/* Registers other than the WDTINT is always synchronized with WDT_CLK */
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if (reg != WDTINT)
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rzg2l_wdt_wait_delay(priv);
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}
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static void rzg2l_wdt_init_timeout(struct watchdog_device *wdev)
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{
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struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
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u32 time_out;
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/* Clear Lapsed Time Register and clear Interrupt */
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rzg2l_wdt_write(priv, WDTINT_INTDISP, WDTINT);
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/* 2 consecutive overflow cycle needed to trigger reset */
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time_out = (wdev->timeout * (MICRO / 2)) /
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rzg2l_wdt_get_cycle_usec(priv->osc_clk_rate, 0);
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rzg2l_wdt_write(priv, WDTSET_COUNTER_VAL(time_out), WDTSET);
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}
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static int rzg2l_wdt_start(struct watchdog_device *wdev)
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{
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struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
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pm_runtime_get_sync(wdev->parent);
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/* Initialize time out */
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rzg2l_wdt_init_timeout(wdev);
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/* Initialize watchdog counter register */
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rzg2l_wdt_write(priv, 0, WDTTIM);
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/* Enable watchdog timer*/
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rzg2l_wdt_write(priv, WDTCNT_WDTEN, WDTCNT);
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return 0;
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}
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static int rzg2l_wdt_stop(struct watchdog_device *wdev)
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{
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struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
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rzg2l_wdt_reset(priv);
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pm_runtime_put(wdev->parent);
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return 0;
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}
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static int rzg2l_wdt_set_timeout(struct watchdog_device *wdev, unsigned int timeout)
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{
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wdev->timeout = timeout;
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/*
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* If the watchdog is active, reset the module for updating the WDTSET
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* register by calling rzg2l_wdt_stop() (which internally calls reset_control_reset()
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* to reset the module) so that it is updated with new timeout values.
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*/
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if (watchdog_active(wdev)) {
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rzg2l_wdt_stop(wdev);
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rzg2l_wdt_start(wdev);
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}
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return 0;
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}
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static int rzg2l_wdt_restart(struct watchdog_device *wdev,
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unsigned long action, void *data)
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{
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struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
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clk_prepare_enable(priv->pclk);
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clk_prepare_enable(priv->osc_clk);
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if (priv->devtype == WDT_RZG2L) {
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/* Generate Reset (WDTRSTB) Signal on parity error */
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rzg2l_wdt_write(priv, 0, PECR);
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/* Force parity error */
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rzg2l_wdt_write(priv, PEEN_FORCE, PEEN);
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} else {
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/* RZ/V2M doesn't have parity error registers */
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rzg2l_wdt_reset(priv);
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wdev->timeout = 0;
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/* Initialize time out */
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rzg2l_wdt_init_timeout(wdev);
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/* Initialize watchdog counter register */
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rzg2l_wdt_write(priv, 0, WDTTIM);
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/* Enable watchdog timer*/
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rzg2l_wdt_write(priv, WDTCNT_WDTEN, WDTCNT);
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/* Wait 2 consecutive overflow cycles for reset */
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mdelay(DIV_ROUND_UP(2 * 0xFFFFF * 1000, priv->osc_clk_rate));
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}
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return 0;
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}
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static const struct watchdog_info rzg2l_wdt_ident = {
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.options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
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.identity = "Renesas RZ/G2L WDT Watchdog",
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};
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static int rzg2l_wdt_ping(struct watchdog_device *wdev)
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{
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struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
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rzg2l_wdt_write(priv, WDTINT_INTDISP, WDTINT);
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return 0;
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}
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static const struct watchdog_ops rzg2l_wdt_ops = {
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.owner = THIS_MODULE,
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.start = rzg2l_wdt_start,
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.stop = rzg2l_wdt_stop,
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.ping = rzg2l_wdt_ping,
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.set_timeout = rzg2l_wdt_set_timeout,
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.restart = rzg2l_wdt_restart,
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};
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static void rzg2l_wdt_reset_assert_pm_disable(void *data)
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{
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struct watchdog_device *wdev = data;
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struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
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pm_runtime_disable(wdev->parent);
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reset_control_assert(priv->rstc);
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}
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static int rzg2l_wdt_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct rzg2l_wdt_priv *priv;
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unsigned long pclk_rate;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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/* Get watchdog main clock */
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priv->osc_clk = devm_clk_get(&pdev->dev, "oscclk");
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if (IS_ERR(priv->osc_clk))
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return dev_err_probe(&pdev->dev, PTR_ERR(priv->osc_clk), "no oscclk");
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priv->osc_clk_rate = clk_get_rate(priv->osc_clk);
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if (!priv->osc_clk_rate)
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return dev_err_probe(&pdev->dev, -EINVAL, "oscclk rate is 0");
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/* Get Peripheral clock */
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priv->pclk = devm_clk_get(&pdev->dev, "pclk");
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if (IS_ERR(priv->pclk))
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return dev_err_probe(&pdev->dev, PTR_ERR(priv->pclk), "no pclk");
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pclk_rate = clk_get_rate(priv->pclk);
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if (!pclk_rate)
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return dev_err_probe(&pdev->dev, -EINVAL, "pclk rate is 0");
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priv->delay = F2CYCLE_NSEC(priv->osc_clk_rate) * 6 + F2CYCLE_NSEC(pclk_rate) * 9;
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priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
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if (IS_ERR(priv->rstc))
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return dev_err_probe(&pdev->dev, PTR_ERR(priv->rstc),
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"failed to get cpg reset");
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ret = reset_control_deassert(priv->rstc);
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if (ret)
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return dev_err_probe(dev, ret, "failed to deassert");
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priv->devtype = (uintptr_t)of_device_get_match_data(dev);
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if (priv->devtype == WDT_RZV2M) {
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priv->minimum_assertion_period = RZV2M_A_NSEC +
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3 * F2CYCLE_NSEC(pclk_rate) + 5 *
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max(F2CYCLE_NSEC(priv->osc_clk_rate),
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F2CYCLE_NSEC(pclk_rate));
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}
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pm_runtime_enable(&pdev->dev);
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priv->wdev.info = &rzg2l_wdt_ident;
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priv->wdev.ops = &rzg2l_wdt_ops;
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priv->wdev.parent = dev;
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priv->wdev.min_timeout = 1;
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priv->wdev.max_timeout = rzg2l_wdt_get_cycle_usec(priv->osc_clk_rate, 0xfff) /
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USEC_PER_SEC;
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priv->wdev.timeout = WDT_DEFAULT_TIMEOUT;
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watchdog_set_drvdata(&priv->wdev, priv);
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ret = devm_add_action_or_reset(&pdev->dev,
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rzg2l_wdt_reset_assert_pm_disable,
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&priv->wdev);
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if (ret < 0)
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return ret;
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watchdog_set_nowayout(&priv->wdev, nowayout);
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watchdog_stop_on_unregister(&priv->wdev);
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ret = watchdog_init_timeout(&priv->wdev, 0, dev);
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if (ret)
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dev_warn(dev, "Specified timeout invalid, using default");
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return devm_watchdog_register_device(&pdev->dev, &priv->wdev);
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}
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static const struct of_device_id rzg2l_wdt_ids[] = {
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{ .compatible = "renesas,rzg2l-wdt", .data = (void *)WDT_RZG2L },
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{ .compatible = "renesas,rzv2m-wdt", .data = (void *)WDT_RZV2M },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, rzg2l_wdt_ids);
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static struct platform_driver rzg2l_wdt_driver = {
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.driver = {
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.name = "rzg2l_wdt",
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.of_match_table = rzg2l_wdt_ids,
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},
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.probe = rzg2l_wdt_probe,
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};
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module_platform_driver(rzg2l_wdt_driver);
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MODULE_DESCRIPTION("Renesas RZ/G2L WDT Watchdog Driver");
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MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
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MODULE_LICENSE("GPL v2");
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