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![Nathan Chancellor](/assets/img/avatar_default.png)
After commit f1a43aadb5
("watchdog: Enable COMPILE_TEST for more
drivers"), it is possible to enable this driver on 32-bit architectures.
When building for those architectures with clang, there is an error due
to a 64-bit division in xilinx_wwdt_start():
ERROR: modpost: "__aeabi_uldivmod" [drivers/watchdog/xilinx_wwdt.ko] undefined!
Use div_u64() to fix this, which takes a 64-bit dividend and 32-bit
divisor. GCC likely avoids the same error due to optimizations it
employs to transform division by a constant into other equivalent
operations, which may be different than what is implemented in clang.
Link: https://github.com/ClangBuiltLinux/linux/issues/1915
Signed-off-by: Nathan Chancellor <nathan@kernel.org>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20230815-watchdog-xilinx-div_u64-v1-1-20b0b5a65c2e@kernel.org
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
202 lines
5.6 KiB
C
202 lines
5.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Window watchdog device driver for Xilinx Versal WWDT
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*
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* Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
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*/
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/math64.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/watchdog.h>
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/* Max timeout is calculated at 100MHz source clock */
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#define XWWDT_DEFAULT_TIMEOUT 42
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#define XWWDT_MIN_TIMEOUT 1
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/* Register offsets for the WWDT device */
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#define XWWDT_MWR_OFFSET 0x00
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#define XWWDT_ESR_OFFSET 0x04
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#define XWWDT_FCR_OFFSET 0x08
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#define XWWDT_FWR_OFFSET 0x0c
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#define XWWDT_SWR_OFFSET 0x10
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/* Master Write Control Register Masks */
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#define XWWDT_MWR_MASK BIT(0)
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/* Enable and Status Register Masks */
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#define XWWDT_ESR_WINT_MASK BIT(16)
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#define XWWDT_ESR_WSW_MASK BIT(8)
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#define XWWDT_ESR_WEN_MASK BIT(0)
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#define XWWDT_CLOSE_WINDOW_PERCENT 50
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static int wwdt_timeout;
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static int closed_window_percent;
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module_param(wwdt_timeout, int, 0);
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MODULE_PARM_DESC(wwdt_timeout,
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"Watchdog time in seconds. (default="
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__MODULE_STRING(XWWDT_DEFAULT_TIMEOUT) ")");
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module_param(closed_window_percent, int, 0);
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MODULE_PARM_DESC(closed_window_percent,
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"Watchdog closed window percentage. (default="
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__MODULE_STRING(XWWDT_CLOSE_WINDOW_PERCENT) ")");
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/**
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* struct xwwdt_device - Watchdog device structure
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* @base: base io address of WDT device
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* @spinlock: spinlock for IO register access
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* @xilinx_wwdt_wdd: watchdog device structure
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* @freq: source clock frequency of WWDT
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* @close_percent: Closed window percent
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*/
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struct xwwdt_device {
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void __iomem *base;
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spinlock_t spinlock; /* spinlock for register handling */
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struct watchdog_device xilinx_wwdt_wdd;
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unsigned long freq;
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u32 close_percent;
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};
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static int xilinx_wwdt_start(struct watchdog_device *wdd)
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{
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struct xwwdt_device *xdev = watchdog_get_drvdata(wdd);
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struct watchdog_device *xilinx_wwdt_wdd = &xdev->xilinx_wwdt_wdd;
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u64 time_out, closed_timeout, open_timeout;
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u32 control_status_reg;
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/* Calculate timeout count */
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time_out = xdev->freq * wdd->timeout;
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closed_timeout = div_u64(time_out * xdev->close_percent, 100);
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open_timeout = time_out - closed_timeout;
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wdd->min_hw_heartbeat_ms = xdev->close_percent * 10 * wdd->timeout;
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spin_lock(&xdev->spinlock);
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iowrite32(XWWDT_MWR_MASK, xdev->base + XWWDT_MWR_OFFSET);
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iowrite32(~(u32)XWWDT_ESR_WEN_MASK, xdev->base + XWWDT_ESR_OFFSET);
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iowrite32((u32)closed_timeout, xdev->base + XWWDT_FWR_OFFSET);
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iowrite32((u32)open_timeout, xdev->base + XWWDT_SWR_OFFSET);
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/* Enable the window watchdog timer */
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control_status_reg = ioread32(xdev->base + XWWDT_ESR_OFFSET);
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control_status_reg |= XWWDT_ESR_WEN_MASK;
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iowrite32(control_status_reg, xdev->base + XWWDT_ESR_OFFSET);
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spin_unlock(&xdev->spinlock);
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dev_dbg(xilinx_wwdt_wdd->parent, "Watchdog Started!\n");
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return 0;
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}
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static int xilinx_wwdt_keepalive(struct watchdog_device *wdd)
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{
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struct xwwdt_device *xdev = watchdog_get_drvdata(wdd);
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u32 control_status_reg;
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spin_lock(&xdev->spinlock);
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/* Enable write access control bit for the window watchdog */
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iowrite32(XWWDT_MWR_MASK, xdev->base + XWWDT_MWR_OFFSET);
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/* Trigger restart kick to watchdog */
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control_status_reg = ioread32(xdev->base + XWWDT_ESR_OFFSET);
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control_status_reg |= XWWDT_ESR_WSW_MASK;
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iowrite32(control_status_reg, xdev->base + XWWDT_ESR_OFFSET);
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spin_unlock(&xdev->spinlock);
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return 0;
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}
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static const struct watchdog_info xilinx_wwdt_ident = {
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.options = WDIOF_KEEPALIVEPING |
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WDIOF_SETTIMEOUT,
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.firmware_version = 1,
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.identity = "xlnx_window watchdog",
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};
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static const struct watchdog_ops xilinx_wwdt_ops = {
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.owner = THIS_MODULE,
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.start = xilinx_wwdt_start,
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.ping = xilinx_wwdt_keepalive,
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};
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static int xwwdt_probe(struct platform_device *pdev)
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{
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struct watchdog_device *xilinx_wwdt_wdd;
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struct device *dev = &pdev->dev;
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struct xwwdt_device *xdev;
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struct clk *clk;
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int ret;
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xdev = devm_kzalloc(dev, sizeof(*xdev), GFP_KERNEL);
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if (!xdev)
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return -ENOMEM;
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xilinx_wwdt_wdd = &xdev->xilinx_wwdt_wdd;
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xilinx_wwdt_wdd->info = &xilinx_wwdt_ident;
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xilinx_wwdt_wdd->ops = &xilinx_wwdt_ops;
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xilinx_wwdt_wdd->parent = dev;
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xdev->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(xdev->base))
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return PTR_ERR(xdev->base);
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clk = devm_clk_get_enabled(dev, NULL);
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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xdev->freq = clk_get_rate(clk);
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if (!xdev->freq)
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return -EINVAL;
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xilinx_wwdt_wdd->min_timeout = XWWDT_MIN_TIMEOUT;
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xilinx_wwdt_wdd->timeout = XWWDT_DEFAULT_TIMEOUT;
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xilinx_wwdt_wdd->max_hw_heartbeat_ms = 1000 * xilinx_wwdt_wdd->timeout;
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if (closed_window_percent == 0 || closed_window_percent >= 100)
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xdev->close_percent = XWWDT_CLOSE_WINDOW_PERCENT;
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else
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xdev->close_percent = closed_window_percent;
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watchdog_init_timeout(xilinx_wwdt_wdd, wwdt_timeout, &pdev->dev);
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spin_lock_init(&xdev->spinlock);
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watchdog_set_drvdata(xilinx_wwdt_wdd, xdev);
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watchdog_set_nowayout(xilinx_wwdt_wdd, 1);
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ret = devm_watchdog_register_device(dev, xilinx_wwdt_wdd);
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if (ret)
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return ret;
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dev_info(dev, "Xilinx window watchdog Timer with timeout %ds\n",
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xilinx_wwdt_wdd->timeout);
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return 0;
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}
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static const struct of_device_id xwwdt_of_match[] = {
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{ .compatible = "xlnx,versal-wwdt", },
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{},
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};
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MODULE_DEVICE_TABLE(of, xwwdt_of_match);
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static struct platform_driver xwwdt_driver = {
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.probe = xwwdt_probe,
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.driver = {
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.name = "Xilinx window watchdog",
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.of_match_table = xwwdt_of_match,
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},
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};
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module_platform_driver(xwwdt_driver);
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MODULE_AUTHOR("Neeli Srinivas <srinivas.neeli@amd.com>");
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MODULE_DESCRIPTION("Xilinx window watchdog driver");
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MODULE_LICENSE("GPL");
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