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Delta TN48M CPLD exposes resets for the following: * 88F7040 SoC * 88F6820 SoC * 98DX3265 switch MAC-s * 88E1680 PHY-s * 88E1512 PHY * PoE PSE controller Controller supports only self clearing resets. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Robert Marko <robert.marko@sartura.hr> Link: https://lore.kernel.org/r/20220131133049.77780-5-robert.marko@sartura.hr Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
128 lines
2.9 KiB
C
128 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Delta TN48M CPLD reset driver
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*
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* Copyright (C) 2021 Sartura Ltd.
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*
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* Author: Robert Marko <robert.marko@sartura.hr>
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*/
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/reset-controller.h>
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#include <dt-bindings/reset/delta,tn48m-reset.h>
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#define TN48M_RESET_REG 0x10
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#define TN48M_RESET_TIMEOUT_US 125000
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#define TN48M_RESET_SLEEP_US 10
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struct tn48_reset_map {
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u8 bit;
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};
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struct tn48_reset_data {
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struct reset_controller_dev rcdev;
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struct regmap *regmap;
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};
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static const struct tn48_reset_map tn48m_resets[] = {
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[CPU_88F7040_RESET] = {0},
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[CPU_88F6820_RESET] = {1},
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[MAC_98DX3265_RESET] = {2},
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[PHY_88E1680_RESET] = {4},
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[PHY_88E1512_RESET] = {6},
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[POE_RESET] = {7},
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};
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static inline struct tn48_reset_data *to_tn48_reset_data(
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struct reset_controller_dev *rcdev)
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{
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return container_of(rcdev, struct tn48_reset_data, rcdev);
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}
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static int tn48m_control_reset(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct tn48_reset_data *data = to_tn48_reset_data(rcdev);
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unsigned int val;
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regmap_update_bits(data->regmap, TN48M_RESET_REG,
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BIT(tn48m_resets[id].bit), 0);
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return regmap_read_poll_timeout(data->regmap,
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TN48M_RESET_REG,
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val,
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val & BIT(tn48m_resets[id].bit),
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TN48M_RESET_SLEEP_US,
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TN48M_RESET_TIMEOUT_US);
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}
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static int tn48m_control_status(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct tn48_reset_data *data = to_tn48_reset_data(rcdev);
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unsigned int regval;
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int ret;
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ret = regmap_read(data->regmap, TN48M_RESET_REG, ®val);
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if (ret < 0)
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return ret;
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if (BIT(tn48m_resets[id].bit) & regval)
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return 0;
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else
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return 1;
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}
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static const struct reset_control_ops tn48_reset_ops = {
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.reset = tn48m_control_reset,
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.status = tn48m_control_status,
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};
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static int tn48m_reset_probe(struct platform_device *pdev)
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{
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struct tn48_reset_data *data;
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struct regmap *regmap;
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regmap = dev_get_regmap(pdev->dev.parent, NULL);
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if (!regmap)
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return -ENODEV;
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data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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data->regmap = regmap;
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data->rcdev.owner = THIS_MODULE;
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data->rcdev.ops = &tn48_reset_ops;
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data->rcdev.nr_resets = ARRAY_SIZE(tn48m_resets);
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data->rcdev.of_node = pdev->dev.of_node;
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return devm_reset_controller_register(&pdev->dev, &data->rcdev);
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}
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static const struct of_device_id tn48m_reset_of_match[] = {
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{ .compatible = "delta,tn48m-reset" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, tn48m_reset_of_match);
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static struct platform_driver tn48m_reset_driver = {
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.driver = {
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.name = "delta-tn48m-reset",
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.of_match_table = tn48m_reset_of_match,
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},
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.probe = tn48m_reset_probe,
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};
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module_platform_driver(tn48m_reset_driver);
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MODULE_AUTHOR("Robert Marko <robert.marko@sartura.hr>");
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MODULE_DESCRIPTION("Delta TN48M CPLD reset driver");
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MODULE_LICENSE("GPL");
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