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![Tuomas Tynkkynen](/assets/img/avatar_default.png)
The Tegra124 will use a different driver for frequency scaling, so rename the old driver (which handles only Tegra20) appropriately. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
218 lines
5.6 KiB
C
218 lines
5.6 KiB
C
/*
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* Copyright (C) 2010 Google, Inc.
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*
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* Author:
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* Colin Cross <ccross@google.com>
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* Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/sched.h>
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#include <linux/cpufreq.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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static struct cpufreq_frequency_table freq_table[] = {
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{ .frequency = 216000 },
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{ .frequency = 312000 },
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{ .frequency = 456000 },
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{ .frequency = 608000 },
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{ .frequency = 760000 },
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{ .frequency = 816000 },
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{ .frequency = 912000 },
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{ .frequency = 1000000 },
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{ .frequency = CPUFREQ_TABLE_END },
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};
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#define NUM_CPUS 2
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static struct clk *cpu_clk;
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static struct clk *pll_x_clk;
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static struct clk *pll_p_clk;
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static struct clk *emc_clk;
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static bool pll_x_prepared;
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static unsigned int tegra_get_intermediate(struct cpufreq_policy *policy,
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unsigned int index)
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{
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unsigned int ifreq = clk_get_rate(pll_p_clk) / 1000;
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/*
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* Don't switch to intermediate freq if:
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* - we are already at it, i.e. policy->cur == ifreq
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* - index corresponds to ifreq
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*/
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if ((freq_table[index].frequency == ifreq) || (policy->cur == ifreq))
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return 0;
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return ifreq;
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}
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static int tegra_target_intermediate(struct cpufreq_policy *policy,
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unsigned int index)
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{
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int ret;
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/*
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* Take an extra reference to the main pll so it doesn't turn
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* off when we move the cpu off of it as enabling it again while we
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* switch to it from tegra_target() would take additional time.
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*
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* When target-freq is equal to intermediate freq we don't need to
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* switch to an intermediate freq and so this routine isn't called.
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* Also, we wouldn't be using pll_x anymore and must not take extra
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* reference to it, as it can be disabled now to save some power.
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*/
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clk_prepare_enable(pll_x_clk);
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ret = clk_set_parent(cpu_clk, pll_p_clk);
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if (ret)
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clk_disable_unprepare(pll_x_clk);
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else
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pll_x_prepared = true;
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return ret;
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}
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static int tegra_target(struct cpufreq_policy *policy, unsigned int index)
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{
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unsigned long rate = freq_table[index].frequency;
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unsigned int ifreq = clk_get_rate(pll_p_clk) / 1000;
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int ret = 0;
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/*
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* Vote on memory bus frequency based on cpu frequency
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* This sets the minimum frequency, display or avp may request higher
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*/
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if (rate >= 816000)
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clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */
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else if (rate >= 456000)
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clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */
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else
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clk_set_rate(emc_clk, 100000000); /* emc 50Mhz */
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/*
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* target freq == pll_p, don't need to take extra reference to pll_x_clk
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* as it isn't used anymore.
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*/
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if (rate == ifreq)
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return clk_set_parent(cpu_clk, pll_p_clk);
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ret = clk_set_rate(pll_x_clk, rate * 1000);
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/* Restore to earlier frequency on error, i.e. pll_x */
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if (ret)
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pr_err("Failed to change pll_x to %lu\n", rate);
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ret = clk_set_parent(cpu_clk, pll_x_clk);
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/* This shouldn't fail while changing or restoring */
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WARN_ON(ret);
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/*
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* Drop count to pll_x clock only if we switched to intermediate freq
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* earlier while transitioning to a target frequency.
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*/
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if (pll_x_prepared) {
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clk_disable_unprepare(pll_x_clk);
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pll_x_prepared = false;
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}
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return ret;
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}
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static int tegra_cpu_init(struct cpufreq_policy *policy)
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{
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int ret;
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if (policy->cpu >= NUM_CPUS)
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return -EINVAL;
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clk_prepare_enable(emc_clk);
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clk_prepare_enable(cpu_clk);
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/* FIXME: what's the actual transition time? */
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ret = cpufreq_generic_init(policy, freq_table, 300 * 1000);
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if (ret) {
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clk_disable_unprepare(cpu_clk);
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clk_disable_unprepare(emc_clk);
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return ret;
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}
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policy->clk = cpu_clk;
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policy->suspend_freq = freq_table[0].frequency;
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return 0;
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}
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static int tegra_cpu_exit(struct cpufreq_policy *policy)
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{
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clk_disable_unprepare(cpu_clk);
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clk_disable_unprepare(emc_clk);
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return 0;
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}
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static struct cpufreq_driver tegra_cpufreq_driver = {
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.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
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.verify = cpufreq_generic_frequency_table_verify,
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.get_intermediate = tegra_get_intermediate,
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.target_intermediate = tegra_target_intermediate,
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.target_index = tegra_target,
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.get = cpufreq_generic_get,
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.init = tegra_cpu_init,
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.exit = tegra_cpu_exit,
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.name = "tegra",
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.attr = cpufreq_generic_attr,
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#ifdef CONFIG_PM
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.suspend = cpufreq_generic_suspend,
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#endif
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};
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static int __init tegra_cpufreq_init(void)
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{
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cpu_clk = clk_get_sys(NULL, "cclk");
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if (IS_ERR(cpu_clk))
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return PTR_ERR(cpu_clk);
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pll_x_clk = clk_get_sys(NULL, "pll_x");
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if (IS_ERR(pll_x_clk))
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return PTR_ERR(pll_x_clk);
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pll_p_clk = clk_get_sys(NULL, "pll_p");
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if (IS_ERR(pll_p_clk))
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return PTR_ERR(pll_p_clk);
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emc_clk = clk_get_sys("cpu", "emc");
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if (IS_ERR(emc_clk)) {
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clk_put(cpu_clk);
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return PTR_ERR(emc_clk);
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}
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return cpufreq_register_driver(&tegra_cpufreq_driver);
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}
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static void __exit tegra_cpufreq_exit(void)
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{
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cpufreq_unregister_driver(&tegra_cpufreq_driver);
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clk_put(emc_clk);
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clk_put(cpu_clk);
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}
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MODULE_AUTHOR("Colin Cross <ccross@android.com>");
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MODULE_DESCRIPTION("cpufreq driver for Nvidia Tegra2");
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MODULE_LICENSE("GPL");
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module_init(tegra_cpufreq_init);
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module_exit(tegra_cpufreq_exit);
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