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![Thomas Gleixner](/assets/img/avatar_default.png)
The irq argument of most interrupt flow handlers is unused or merily used instead of a local variable. The handlers which need the irq argument can retrieve the irq number from the irq descriptor. Search and update was done with coccinelle and the invaluable help of Julia Lawall. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Jiang Liu <jiang.liu@linux.intel.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org
807 lines
21 KiB
C
807 lines
21 KiB
C
/*
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* U300 GPIO module.
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*
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* Copyright (C) 2007-2012 ST-Ericsson AB
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* License terms: GNU General Public License (GPL) version 2
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* COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
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* Author: Linus Walleij <linus.walleij@linaro.org>
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* Author: Jonas Aaberg <jonas.aberg@stericsson.com>
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*/
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/gpio.h>
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#include <linux/slab.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include "pinctrl-coh901.h"
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#define U300_GPIO_PORT_STRIDE (0x30)
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/*
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* Control Register 32bit (R/W)
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* bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
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* gives the number of GPIO pins.
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* bit 8-2 (mask 0x000001FC) contains the core version ID.
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*/
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#define U300_GPIO_CR (0x00)
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#define U300_GPIO_CR_SYNC_SEL_ENABLE (0x00000002UL)
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#define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL)
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#define U300_GPIO_PXPDIR (0x04)
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#define U300_GPIO_PXPDOR (0x08)
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#define U300_GPIO_PXPCR (0x0C)
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#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL)
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#define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL)
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#define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL)
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#define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL)
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#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL)
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#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL)
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#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL)
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#define U300_GPIO_PXPER (0x10)
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#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
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#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
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#define U300_GPIO_PXIEV (0x14)
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#define U300_GPIO_PXIEN (0x18)
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#define U300_GPIO_PXIFR (0x1C)
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#define U300_GPIO_PXICR (0x20)
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#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL)
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#define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL)
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#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL)
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#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL)
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/* 8 bits per port, no version has more than 7 ports */
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#define U300_GPIO_NUM_PORTS 7
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#define U300_GPIO_PINS_PER_PORT 8
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#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS)
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struct u300_gpio_port {
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struct u300_gpio *gpio;
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char name[8];
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int irq;
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int number;
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u8 toggle_edge_mode;
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};
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struct u300_gpio {
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struct gpio_chip chip;
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struct u300_gpio_port ports[U300_GPIO_NUM_PORTS];
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struct clk *clk;
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void __iomem *base;
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struct device *dev;
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u32 stride;
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/* Register offsets */
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u32 pcr;
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u32 dor;
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u32 dir;
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u32 per;
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u32 icr;
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u32 ien;
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u32 iev;
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};
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/*
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* Macro to expand to read a specific register found in the "gpio"
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* struct. It requires the struct u300_gpio *gpio variable to exist in
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* its context. It calculates the port offset from the given pin
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* offset, muliplies by the port stride and adds the register offset
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* so it provides a pointer to the desired register.
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*/
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#define U300_PIN_REG(pin, reg) \
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(gpio->base + (pin >> 3) * gpio->stride + gpio->reg)
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/*
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* Provides a bitmask for a specific gpio pin inside an 8-bit GPIO
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* register.
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*/
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#define U300_PIN_BIT(pin) \
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(1 << (pin & 0x07))
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struct u300_gpio_confdata {
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u16 bias_mode;
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bool output;
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int outval;
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};
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#define U300_FLOATING_INPUT { \
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.bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \
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.output = false, \
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}
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#define U300_PULL_UP_INPUT { \
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.bias_mode = PIN_CONFIG_BIAS_PULL_UP, \
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.output = false, \
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}
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#define U300_OUTPUT_LOW { \
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.output = true, \
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.outval = 0, \
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}
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#define U300_OUTPUT_HIGH { \
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.output = true, \
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.outval = 1, \
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}
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/* Initial configuration */
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static const struct __initconst u300_gpio_confdata
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bs335_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
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/* Port 0, pins 0-7 */
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{
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U300_FLOATING_INPUT,
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U300_OUTPUT_HIGH,
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U300_FLOATING_INPUT,
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U300_OUTPUT_LOW,
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U300_OUTPUT_LOW,
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U300_OUTPUT_LOW,
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U300_OUTPUT_LOW,
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U300_OUTPUT_LOW,
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},
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/* Port 1, pins 0-7 */
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{
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U300_OUTPUT_LOW,
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U300_OUTPUT_LOW,
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U300_OUTPUT_LOW,
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U300_PULL_UP_INPUT,
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U300_FLOATING_INPUT,
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U300_OUTPUT_HIGH,
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U300_OUTPUT_LOW,
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U300_OUTPUT_LOW,
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},
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/* Port 2, pins 0-7 */
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{
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U300_FLOATING_INPUT,
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U300_FLOATING_INPUT,
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U300_FLOATING_INPUT,
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U300_FLOATING_INPUT,
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U300_OUTPUT_LOW,
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U300_PULL_UP_INPUT,
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U300_OUTPUT_LOW,
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U300_PULL_UP_INPUT,
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},
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/* Port 3, pins 0-7 */
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{
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U300_PULL_UP_INPUT,
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U300_OUTPUT_LOW,
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U300_FLOATING_INPUT,
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U300_FLOATING_INPUT,
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U300_FLOATING_INPUT,
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U300_FLOATING_INPUT,
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U300_FLOATING_INPUT,
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U300_FLOATING_INPUT,
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},
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/* Port 4, pins 0-7 */
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{
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U300_FLOATING_INPUT,
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U300_FLOATING_INPUT,
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U300_FLOATING_INPUT,
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U300_FLOATING_INPUT,
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U300_FLOATING_INPUT,
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U300_FLOATING_INPUT,
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U300_FLOATING_INPUT,
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U300_FLOATING_INPUT,
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},
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/* Port 5, pins 0-7 */
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{
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U300_FLOATING_INPUT,
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U300_FLOATING_INPUT,
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U300_FLOATING_INPUT,
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U300_FLOATING_INPUT,
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U300_FLOATING_INPUT,
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U300_FLOATING_INPUT,
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U300_FLOATING_INPUT,
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U300_FLOATING_INPUT,
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},
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/* Port 6, pind 0-7 */
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{
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U300_FLOATING_INPUT,
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U300_FLOATING_INPUT,
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U300_FLOATING_INPUT,
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U300_FLOATING_INPUT,
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U300_FLOATING_INPUT,
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U300_FLOATING_INPUT,
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U300_FLOATING_INPUT,
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U300_FLOATING_INPUT,
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}
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};
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/**
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* to_u300_gpio() - get the pointer to u300_gpio
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* @chip: the gpio chip member of the structure u300_gpio
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*/
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static inline struct u300_gpio *to_u300_gpio(struct gpio_chip *chip)
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{
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return container_of(chip, struct u300_gpio, chip);
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}
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static int u300_gpio_request(struct gpio_chip *chip, unsigned offset)
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{
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/*
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* Map back to global GPIO space and request muxing, the direction
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* parameter does not matter for this controller.
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*/
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int gpio = chip->base + offset;
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return pinctrl_request_gpio(gpio);
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}
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static void u300_gpio_free(struct gpio_chip *chip, unsigned offset)
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{
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int gpio = chip->base + offset;
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pinctrl_free_gpio(gpio);
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}
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static int u300_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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struct u300_gpio *gpio = to_u300_gpio(chip);
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return readl(U300_PIN_REG(offset, dir)) & U300_PIN_BIT(offset);
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}
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static void u300_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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struct u300_gpio *gpio = to_u300_gpio(chip);
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unsigned long flags;
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u32 val;
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local_irq_save(flags);
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val = readl(U300_PIN_REG(offset, dor));
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if (value)
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writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
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else
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writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
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local_irq_restore(flags);
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}
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static int u300_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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struct u300_gpio *gpio = to_u300_gpio(chip);
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unsigned long flags;
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u32 val;
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local_irq_save(flags);
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val = readl(U300_PIN_REG(offset, pcr));
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/* Mask out this pin, note 2 bits per setting */
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val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
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writel(val, U300_PIN_REG(offset, pcr));
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local_irq_restore(flags);
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return 0;
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}
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static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
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int value)
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{
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struct u300_gpio *gpio = to_u300_gpio(chip);
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unsigned long flags;
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u32 oldmode;
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u32 val;
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local_irq_save(flags);
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val = readl(U300_PIN_REG(offset, pcr));
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/*
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* Drive mode must be set by the special mode set function, set
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* push/pull mode by default if no mode has been selected.
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*/
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oldmode = val & (U300_GPIO_PXPCR_PIN_MODE_MASK <<
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((offset & 0x07) << 1));
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/* mode = 0 means input, else some mode is already set */
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if (oldmode == 0) {
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val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK <<
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((offset & 0x07) << 1));
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val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
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<< ((offset & 0x07) << 1));
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writel(val, U300_PIN_REG(offset, pcr));
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}
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u300_gpio_set(chip, offset, value);
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local_irq_restore(flags);
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return 0;
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}
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/* Returning -EINVAL means "supported but not available" */
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int u300_gpio_config_get(struct gpio_chip *chip,
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unsigned offset,
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unsigned long *config)
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{
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struct u300_gpio *gpio = to_u300_gpio(chip);
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enum pin_config_param param = (enum pin_config_param) *config;
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bool biasmode;
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u32 drmode;
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/* One bit per pin, clamp to bool range */
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biasmode = !!(readl(U300_PIN_REG(offset, per)) & U300_PIN_BIT(offset));
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/* Mask out the two bits for this pin and shift to bits 0,1 */
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drmode = readl(U300_PIN_REG(offset, pcr));
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drmode &= (U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
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drmode >>= ((offset & 0x07) << 1);
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switch (param) {
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case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
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*config = 0;
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if (biasmode)
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return 0;
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else
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return -EINVAL;
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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*config = 0;
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if (!biasmode)
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return 0;
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else
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return -EINVAL;
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break;
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case PIN_CONFIG_DRIVE_PUSH_PULL:
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*config = 0;
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if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL)
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return 0;
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else
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return -EINVAL;
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break;
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case PIN_CONFIG_DRIVE_OPEN_DRAIN:
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*config = 0;
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if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN)
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return 0;
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else
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return -EINVAL;
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break;
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case PIN_CONFIG_DRIVE_OPEN_SOURCE:
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*config = 0;
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if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE)
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return 0;
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else
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return -EINVAL;
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break;
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default:
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break;
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}
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return -ENOTSUPP;
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}
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int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset,
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enum pin_config_param param)
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{
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struct u300_gpio *gpio = to_u300_gpio(chip);
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unsigned long flags;
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u32 val;
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local_irq_save(flags);
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
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val = readl(U300_PIN_REG(offset, per));
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writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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val = readl(U300_PIN_REG(offset, per));
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writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
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break;
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case PIN_CONFIG_DRIVE_PUSH_PULL:
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val = readl(U300_PIN_REG(offset, pcr));
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val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
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<< ((offset & 0x07) << 1));
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val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
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<< ((offset & 0x07) << 1));
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writel(val, U300_PIN_REG(offset, pcr));
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break;
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case PIN_CONFIG_DRIVE_OPEN_DRAIN:
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val = readl(U300_PIN_REG(offset, pcr));
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val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
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<< ((offset & 0x07) << 1));
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val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN
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<< ((offset & 0x07) << 1));
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writel(val, U300_PIN_REG(offset, pcr));
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break;
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case PIN_CONFIG_DRIVE_OPEN_SOURCE:
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val = readl(U300_PIN_REG(offset, pcr));
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val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
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<< ((offset & 0x07) << 1));
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val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE
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<< ((offset & 0x07) << 1));
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writel(val, U300_PIN_REG(offset, pcr));
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break;
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default:
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local_irq_restore(flags);
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dev_err(gpio->dev, "illegal configuration requested\n");
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return -EINVAL;
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}
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local_irq_restore(flags);
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return 0;
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}
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static struct gpio_chip u300_gpio_chip = {
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.label = "u300-gpio-chip",
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.owner = THIS_MODULE,
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.request = u300_gpio_request,
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.free = u300_gpio_free,
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.get = u300_gpio_get,
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.set = u300_gpio_set,
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.direction_input = u300_gpio_direction_input,
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.direction_output = u300_gpio_direction_output,
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};
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static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset)
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{
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u32 val;
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val = readl(U300_PIN_REG(offset, icr));
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/* Set mode depending on state */
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if (u300_gpio_get(&gpio->chip, offset)) {
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/* High now, let's trigger on falling edge next then */
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writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
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dev_dbg(gpio->dev, "next IRQ on falling edge on pin %d\n",
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offset);
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} else {
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/* Low now, let's trigger on rising edge next then */
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writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
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dev_dbg(gpio->dev, "next IRQ on rising edge on pin %d\n",
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offset);
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}
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}
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static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
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struct u300_gpio *gpio = to_u300_gpio(chip);
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struct u300_gpio_port *port = &gpio->ports[d->hwirq >> 3];
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int offset = d->hwirq;
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u32 val;
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if ((trigger & IRQF_TRIGGER_RISING) &&
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(trigger & IRQF_TRIGGER_FALLING)) {
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/*
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* The GPIO block can only trigger on falling OR rising edges,
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* not both. So we need to toggle the mode whenever the pin
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* goes from one state to the other with a special state flag
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*/
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dev_dbg(gpio->dev,
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"trigger on both rising and falling edge on pin %d\n",
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offset);
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port->toggle_edge_mode |= U300_PIN_BIT(offset);
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u300_toggle_trigger(gpio, offset);
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} else if (trigger & IRQF_TRIGGER_RISING) {
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dev_dbg(gpio->dev, "trigger on rising edge on pin %d\n",
|
|
offset);
|
|
val = readl(U300_PIN_REG(offset, icr));
|
|
writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
|
|
port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
|
|
} else if (trigger & IRQF_TRIGGER_FALLING) {
|
|
dev_dbg(gpio->dev, "trigger on falling edge on pin %d\n",
|
|
offset);
|
|
val = readl(U300_PIN_REG(offset, icr));
|
|
writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
|
|
port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void u300_gpio_irq_enable(struct irq_data *d)
|
|
{
|
|
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
|
|
struct u300_gpio *gpio = to_u300_gpio(chip);
|
|
struct u300_gpio_port *port = &gpio->ports[d->hwirq >> 3];
|
|
int offset = d->hwirq;
|
|
u32 val;
|
|
unsigned long flags;
|
|
|
|
dev_dbg(gpio->dev, "enable IRQ for hwirq %lu on port %s, offset %d\n",
|
|
d->hwirq, port->name, offset);
|
|
local_irq_save(flags);
|
|
val = readl(U300_PIN_REG(offset, ien));
|
|
writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
static void u300_gpio_irq_disable(struct irq_data *d)
|
|
{
|
|
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
|
|
struct u300_gpio *gpio = to_u300_gpio(chip);
|
|
int offset = d->hwirq;
|
|
u32 val;
|
|
unsigned long flags;
|
|
|
|
local_irq_save(flags);
|
|
val = readl(U300_PIN_REG(offset, ien));
|
|
writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
static struct irq_chip u300_gpio_irqchip = {
|
|
.name = "u300-gpio-irqchip",
|
|
.irq_enable = u300_gpio_irq_enable,
|
|
.irq_disable = u300_gpio_irq_disable,
|
|
.irq_set_type = u300_gpio_irq_type,
|
|
};
|
|
|
|
static void u300_gpio_irq_handler(unsigned __irq, struct irq_desc *desc)
|
|
{
|
|
unsigned int irq = irq_desc_get_irq(desc);
|
|
struct irq_chip *parent_chip = irq_desc_get_chip(desc);
|
|
struct gpio_chip *chip = irq_desc_get_handler_data(desc);
|
|
struct u300_gpio *gpio = to_u300_gpio(chip);
|
|
struct u300_gpio_port *port = &gpio->ports[irq - chip->base];
|
|
int pinoffset = port->number << 3; /* get the right stride */
|
|
unsigned long val;
|
|
|
|
chained_irq_enter(parent_chip, desc);
|
|
|
|
/* Read event register */
|
|
val = readl(U300_PIN_REG(pinoffset, iev));
|
|
/* Mask relevant bits */
|
|
val &= 0xFFU; /* 8 bits per port */
|
|
/* ACK IRQ (clear event) */
|
|
writel(val, U300_PIN_REG(pinoffset, iev));
|
|
|
|
/* Call IRQ handler */
|
|
if (val != 0) {
|
|
int irqoffset;
|
|
|
|
for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) {
|
|
int offset = pinoffset + irqoffset;
|
|
int pin_irq = irq_find_mapping(chip->irqdomain, offset);
|
|
|
|
dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n",
|
|
pin_irq, offset);
|
|
generic_handle_irq(pin_irq);
|
|
/*
|
|
* Triggering IRQ on both rising and falling edge
|
|
* needs mockery
|
|
*/
|
|
if (port->toggle_edge_mode & U300_PIN_BIT(offset))
|
|
u300_toggle_trigger(gpio, offset);
|
|
}
|
|
}
|
|
|
|
chained_irq_exit(parent_chip, desc);
|
|
}
|
|
|
|
static void __init u300_gpio_init_pin(struct u300_gpio *gpio,
|
|
int offset,
|
|
const struct u300_gpio_confdata *conf)
|
|
{
|
|
/* Set mode: input or output */
|
|
if (conf->output) {
|
|
u300_gpio_direction_output(&gpio->chip, offset, conf->outval);
|
|
|
|
/* Deactivate bias mode for output */
|
|
u300_gpio_config_set(&gpio->chip, offset,
|
|
PIN_CONFIG_BIAS_HIGH_IMPEDANCE);
|
|
|
|
/* Set drive mode for output */
|
|
u300_gpio_config_set(&gpio->chip, offset,
|
|
PIN_CONFIG_DRIVE_PUSH_PULL);
|
|
|
|
dev_dbg(gpio->dev, "set up pin %d as output, value: %d\n",
|
|
offset, conf->outval);
|
|
} else {
|
|
u300_gpio_direction_input(&gpio->chip, offset);
|
|
|
|
/* Always set output low on input pins */
|
|
u300_gpio_set(&gpio->chip, offset, 0);
|
|
|
|
/* Set bias mode for input */
|
|
u300_gpio_config_set(&gpio->chip, offset, conf->bias_mode);
|
|
|
|
dev_dbg(gpio->dev, "set up pin %d as input, bias: %04x\n",
|
|
offset, conf->bias_mode);
|
|
}
|
|
}
|
|
|
|
static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio)
|
|
{
|
|
int i, j;
|
|
|
|
/* Write default config and values to all pins */
|
|
for (i = 0; i < U300_GPIO_NUM_PORTS; i++) {
|
|
for (j = 0; j < 8; j++) {
|
|
const struct u300_gpio_confdata *conf;
|
|
int offset = (i*8) + j;
|
|
|
|
conf = &bs335_gpio_config[i][j];
|
|
u300_gpio_init_pin(gpio, offset, conf);
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Here we map a GPIO in the local gpio_chip pin space to a pin in
|
|
* the local pinctrl pin space. The pin controller used is
|
|
* pinctrl-u300.
|
|
*/
|
|
struct coh901_pinpair {
|
|
unsigned int offset;
|
|
unsigned int pin_base;
|
|
};
|
|
|
|
#define COH901_PINRANGE(a, b) { .offset = a, .pin_base = b }
|
|
|
|
static struct coh901_pinpair coh901_pintable[] = {
|
|
COH901_PINRANGE(10, 426),
|
|
COH901_PINRANGE(11, 180),
|
|
COH901_PINRANGE(12, 165), /* MS/MMC card insertion */
|
|
COH901_PINRANGE(13, 179),
|
|
COH901_PINRANGE(14, 178),
|
|
COH901_PINRANGE(16, 194),
|
|
COH901_PINRANGE(17, 193),
|
|
COH901_PINRANGE(18, 192),
|
|
COH901_PINRANGE(19, 191),
|
|
COH901_PINRANGE(20, 186),
|
|
COH901_PINRANGE(21, 185),
|
|
COH901_PINRANGE(22, 184),
|
|
COH901_PINRANGE(23, 183),
|
|
COH901_PINRANGE(24, 182),
|
|
COH901_PINRANGE(25, 181),
|
|
};
|
|
|
|
static int __init u300_gpio_probe(struct platform_device *pdev)
|
|
{
|
|
struct u300_gpio *gpio;
|
|
struct resource *memres;
|
|
int err = 0;
|
|
int portno;
|
|
u32 val;
|
|
u32 ifr;
|
|
int i;
|
|
|
|
gpio = devm_kzalloc(&pdev->dev, sizeof(struct u300_gpio), GFP_KERNEL);
|
|
if (gpio == NULL)
|
|
return -ENOMEM;
|
|
|
|
gpio->chip = u300_gpio_chip;
|
|
gpio->chip.ngpio = U300_GPIO_NUM_PORTS * U300_GPIO_PINS_PER_PORT;
|
|
gpio->chip.dev = &pdev->dev;
|
|
gpio->chip.base = 0;
|
|
gpio->dev = &pdev->dev;
|
|
|
|
memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
gpio->base = devm_ioremap_resource(&pdev->dev, memres);
|
|
if (IS_ERR(gpio->base))
|
|
return PTR_ERR(gpio->base);
|
|
|
|
gpio->clk = devm_clk_get(gpio->dev, NULL);
|
|
if (IS_ERR(gpio->clk)) {
|
|
err = PTR_ERR(gpio->clk);
|
|
dev_err(gpio->dev, "could not get GPIO clock\n");
|
|
return err;
|
|
}
|
|
|
|
err = clk_prepare_enable(gpio->clk);
|
|
if (err) {
|
|
dev_err(gpio->dev, "could not enable GPIO clock\n");
|
|
return err;
|
|
}
|
|
|
|
dev_info(gpio->dev,
|
|
"initializing GPIO Controller COH 901 571/3\n");
|
|
gpio->stride = U300_GPIO_PORT_STRIDE;
|
|
gpio->pcr = U300_GPIO_PXPCR;
|
|
gpio->dor = U300_GPIO_PXPDOR;
|
|
gpio->dir = U300_GPIO_PXPDIR;
|
|
gpio->per = U300_GPIO_PXPER;
|
|
gpio->icr = U300_GPIO_PXICR;
|
|
gpio->ien = U300_GPIO_PXIEN;
|
|
gpio->iev = U300_GPIO_PXIEV;
|
|
ifr = U300_GPIO_PXIFR;
|
|
|
|
val = readl(gpio->base + U300_GPIO_CR);
|
|
dev_info(gpio->dev, "COH901571/3 block version: %d, " \
|
|
"number of cores: %d totalling %d pins\n",
|
|
((val & 0x000001FC) >> 2),
|
|
((val & 0x0000FE00) >> 9),
|
|
((val & 0x0000FE00) >> 9) * 8);
|
|
writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE,
|
|
gpio->base + U300_GPIO_CR);
|
|
u300_gpio_init_coh901571(gpio);
|
|
|
|
#ifdef CONFIG_OF_GPIO
|
|
gpio->chip.of_node = pdev->dev.of_node;
|
|
#endif
|
|
err = gpiochip_add(&gpio->chip);
|
|
if (err) {
|
|
dev_err(gpio->dev, "unable to add gpiochip: %d\n", err);
|
|
goto err_no_chip;
|
|
}
|
|
|
|
err = gpiochip_irqchip_add(&gpio->chip,
|
|
&u300_gpio_irqchip,
|
|
0,
|
|
handle_simple_irq,
|
|
IRQ_TYPE_EDGE_FALLING);
|
|
if (err) {
|
|
dev_err(gpio->dev, "no GPIO irqchip\n");
|
|
goto err_no_irqchip;
|
|
}
|
|
|
|
/* Add each port with its IRQ separately */
|
|
for (portno = 0 ; portno < U300_GPIO_NUM_PORTS; portno++) {
|
|
struct u300_gpio_port *port = &gpio->ports[portno];
|
|
|
|
snprintf(port->name, 8, "gpio%d", portno);
|
|
port->number = portno;
|
|
port->gpio = gpio;
|
|
|
|
port->irq = platform_get_irq(pdev, portno);
|
|
|
|
gpiochip_set_chained_irqchip(&gpio->chip,
|
|
&u300_gpio_irqchip,
|
|
port->irq,
|
|
u300_gpio_irq_handler);
|
|
|
|
/* Turns off irq force (test register) for this port */
|
|
writel(0x0, gpio->base + portno * gpio->stride + ifr);
|
|
}
|
|
dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno);
|
|
|
|
/*
|
|
* Add pinctrl pin ranges, the pin controller must be registered
|
|
* at this point
|
|
*/
|
|
for (i = 0; i < ARRAY_SIZE(coh901_pintable); i++) {
|
|
struct coh901_pinpair *p = &coh901_pintable[i];
|
|
|
|
err = gpiochip_add_pin_range(&gpio->chip, "pinctrl-u300",
|
|
p->offset, p->pin_base, 1);
|
|
if (err)
|
|
goto err_no_range;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, gpio);
|
|
|
|
return 0;
|
|
|
|
err_no_range:
|
|
err_no_irqchip:
|
|
gpiochip_remove(&gpio->chip);
|
|
err_no_chip:
|
|
clk_disable_unprepare(gpio->clk);
|
|
dev_err(&pdev->dev, "module ERROR:%d\n", err);
|
|
return err;
|
|
}
|
|
|
|
static int __exit u300_gpio_remove(struct platform_device *pdev)
|
|
{
|
|
struct u300_gpio *gpio = platform_get_drvdata(pdev);
|
|
|
|
/* Turn off the GPIO block */
|
|
writel(0x00000000U, gpio->base + U300_GPIO_CR);
|
|
|
|
gpiochip_remove(&gpio->chip);
|
|
clk_disable_unprepare(gpio->clk);
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id u300_gpio_match[] = {
|
|
{ .compatible = "stericsson,gpio-coh901" },
|
|
{},
|
|
};
|
|
|
|
static struct platform_driver u300_gpio_driver = {
|
|
.driver = {
|
|
.name = "u300-gpio",
|
|
.of_match_table = u300_gpio_match,
|
|
},
|
|
.remove = __exit_p(u300_gpio_remove),
|
|
};
|
|
|
|
static int __init u300_gpio_init(void)
|
|
{
|
|
return platform_driver_probe(&u300_gpio_driver, u300_gpio_probe);
|
|
}
|
|
|
|
static void __exit u300_gpio_exit(void)
|
|
{
|
|
platform_driver_unregister(&u300_gpio_driver);
|
|
}
|
|
|
|
arch_initcall(u300_gpio_init);
|
|
module_exit(u300_gpio_exit);
|
|
|
|
MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
|
|
MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335/COH 901 571/3 GPIO driver");
|
|
MODULE_LICENSE("GPL");
|