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![Toshi Kani](/assets/img/avatar_default.png)
The ghes_edac driver was introduced in 2013 [1], but it has not been enabled by any distro yet. This driver obtains error info from firmware interfaces (APEI), which are not properly implemented on many platforms, as the driver says on load: This EDAC driver relies on BIOS to enumerate memory and get error reports. Unfortunately, not all BIOSes reflect the memory layout correctly. So, the end result of using this driver varies from vendor to vendor. If you find incorrect reports, please contact your hardware vendor to correct its BIOS. To get out from this situation, add a platform check to selectively enable the driver on platforms that are known to have proper APEI firmware implementation. "ghes_edac.force_load=1" skips this platform check. [1]: https://lkml.kernel.org/r/cover.1360931635.git.mchehab@redhat.com Signed-off-by: Toshi Kani <toshi.kani@hpe.com> Cc: Mauro Carvalho Chehab <mchehab@kernel.org> Cc: Tony Luck <tony.luck@intel.com> Cc: linux-acpi@vger.kernel.org Cc: linux-edac <linux-edac@vger.kernel.org> Link: http://lkml.kernel.org/r/20170823225447.15608-4-toshi.kani@hpe.com Signed-off-by: Borislav Petkov <bp@suse.de>
525 lines
13 KiB
C
525 lines
13 KiB
C
/*
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* GHES/EDAC Linux driver
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*
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* This file may be distributed under the terms of the GNU General Public
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* License version 2.
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*
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* Copyright (c) 2013 by Mauro Carvalho Chehab
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*
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* Red Hat Inc. http://www.redhat.com
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <acpi/ghes.h>
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#include <linux/edac.h>
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#include <linux/dmi.h>
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#include "edac_module.h"
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#include <ras/ras_event.h>
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struct ghes_edac_pvt {
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struct list_head list;
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struct ghes *ghes;
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struct mem_ctl_info *mci;
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/* Buffers for the error handling routine */
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char detail_location[240];
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char other_detail[160];
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char msg[80];
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};
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static atomic_t ghes_init = ATOMIC_INIT(0);
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static struct ghes_edac_pvt *ghes_pvt;
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/*
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* Sync with other, potentially concurrent callers of
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* ghes_edac_report_mem_error(). We don't know what the
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* "inventive" firmware would do.
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*/
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static DEFINE_SPINLOCK(ghes_lock);
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/* "ghes_edac.force_load=1" skips the platform check */
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static bool __read_mostly force_load;
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module_param(force_load, bool, 0);
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/* Memory Device - Type 17 of SMBIOS spec */
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struct memdev_dmi_entry {
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u8 type;
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u8 length;
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u16 handle;
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u16 phys_mem_array_handle;
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u16 mem_err_info_handle;
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u16 total_width;
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u16 data_width;
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u16 size;
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u8 form_factor;
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u8 device_set;
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u8 device_locator;
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u8 bank_locator;
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u8 memory_type;
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u16 type_detail;
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u16 speed;
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u8 manufacturer;
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u8 serial_number;
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u8 asset_tag;
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u8 part_number;
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u8 attributes;
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u32 extended_size;
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u16 conf_mem_clk_speed;
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} __attribute__((__packed__));
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struct ghes_edac_dimm_fill {
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struct mem_ctl_info *mci;
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unsigned count;
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};
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static void ghes_edac_count_dimms(const struct dmi_header *dh, void *arg)
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{
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int *num_dimm = arg;
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if (dh->type == DMI_ENTRY_MEM_DEVICE)
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(*num_dimm)++;
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}
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static void ghes_edac_dmidecode(const struct dmi_header *dh, void *arg)
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{
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struct ghes_edac_dimm_fill *dimm_fill = arg;
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struct mem_ctl_info *mci = dimm_fill->mci;
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if (dh->type == DMI_ENTRY_MEM_DEVICE) {
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struct memdev_dmi_entry *entry = (struct memdev_dmi_entry *)dh;
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struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
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mci->n_layers,
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dimm_fill->count, 0, 0);
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if (entry->size == 0xffff) {
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pr_info("Can't get DIMM%i size\n",
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dimm_fill->count);
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dimm->nr_pages = MiB_TO_PAGES(32);/* Unknown */
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} else if (entry->size == 0x7fff) {
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dimm->nr_pages = MiB_TO_PAGES(entry->extended_size);
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} else {
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if (entry->size & 1 << 15)
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dimm->nr_pages = MiB_TO_PAGES((entry->size &
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0x7fff) << 10);
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else
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dimm->nr_pages = MiB_TO_PAGES(entry->size);
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}
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switch (entry->memory_type) {
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case 0x12:
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if (entry->type_detail & 1 << 13)
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dimm->mtype = MEM_RDDR;
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else
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dimm->mtype = MEM_DDR;
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break;
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case 0x13:
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if (entry->type_detail & 1 << 13)
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dimm->mtype = MEM_RDDR2;
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else
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dimm->mtype = MEM_DDR2;
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break;
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case 0x14:
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dimm->mtype = MEM_FB_DDR2;
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break;
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case 0x18:
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if (entry->type_detail & 1 << 13)
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dimm->mtype = MEM_RDDR3;
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else
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dimm->mtype = MEM_DDR3;
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break;
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default:
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if (entry->type_detail & 1 << 6)
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dimm->mtype = MEM_RMBS;
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else if ((entry->type_detail & ((1 << 7) | (1 << 13)))
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== ((1 << 7) | (1 << 13)))
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dimm->mtype = MEM_RDR;
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else if (entry->type_detail & 1 << 7)
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dimm->mtype = MEM_SDR;
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else if (entry->type_detail & 1 << 9)
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dimm->mtype = MEM_EDO;
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else
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dimm->mtype = MEM_UNKNOWN;
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}
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/*
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* Actually, we can only detect if the memory has bits for
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* checksum or not
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*/
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if (entry->total_width == entry->data_width)
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dimm->edac_mode = EDAC_NONE;
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else
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dimm->edac_mode = EDAC_SECDED;
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dimm->dtype = DEV_UNKNOWN;
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dimm->grain = 128; /* Likely, worse case */
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/*
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* FIXME: It shouldn't be hard to also fill the DIMM labels
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*/
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if (dimm->nr_pages) {
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edac_dbg(1, "DIMM%i: %s size = %d MB%s\n",
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dimm_fill->count, edac_mem_types[dimm->mtype],
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PAGES_TO_MiB(dimm->nr_pages),
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(dimm->edac_mode != EDAC_NONE) ? "(ECC)" : "");
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edac_dbg(2, "\ttype %d, detail 0x%02x, width %d(total %d)\n",
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entry->memory_type, entry->type_detail,
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entry->total_width, entry->data_width);
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}
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dimm_fill->count++;
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}
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}
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void ghes_edac_report_mem_error(struct ghes *ghes, int sev,
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struct cper_sec_mem_err *mem_err)
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{
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enum hw_event_mc_err_type type;
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struct edac_raw_error_desc *e;
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struct mem_ctl_info *mci;
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struct ghes_edac_pvt *pvt = ghes_pvt;
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unsigned long flags;
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char *p;
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u8 grain_bits;
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if (!pvt) {
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pr_err("Internal error: Can't find EDAC structure\n");
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return;
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}
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/*
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* We can do the locking below because GHES defers error processing
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* from NMI to IRQ context. Whenever that changes, we'd at least
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* know.
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*/
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if (WARN_ON_ONCE(in_nmi()))
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return;
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spin_lock_irqsave(&ghes_lock, flags);
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mci = pvt->mci;
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e = &mci->error_desc;
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/* Cleans the error report buffer */
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memset(e, 0, sizeof (*e));
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e->error_count = 1;
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strcpy(e->label, "unknown label");
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e->msg = pvt->msg;
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e->other_detail = pvt->other_detail;
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e->top_layer = -1;
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e->mid_layer = -1;
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e->low_layer = -1;
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*pvt->other_detail = '\0';
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*pvt->msg = '\0';
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switch (sev) {
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case GHES_SEV_CORRECTED:
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type = HW_EVENT_ERR_CORRECTED;
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break;
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case GHES_SEV_RECOVERABLE:
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type = HW_EVENT_ERR_UNCORRECTED;
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break;
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case GHES_SEV_PANIC:
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type = HW_EVENT_ERR_FATAL;
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break;
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default:
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case GHES_SEV_NO:
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type = HW_EVENT_ERR_INFO;
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}
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edac_dbg(1, "error validation_bits: 0x%08llx\n",
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(long long)mem_err->validation_bits);
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/* Error type, mapped on e->msg */
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if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_TYPE) {
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p = pvt->msg;
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switch (mem_err->error_type) {
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case 0:
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p += sprintf(p, "Unknown");
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break;
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case 1:
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p += sprintf(p, "No error");
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break;
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case 2:
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p += sprintf(p, "Single-bit ECC");
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break;
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case 3:
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p += sprintf(p, "Multi-bit ECC");
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break;
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case 4:
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p += sprintf(p, "Single-symbol ChipKill ECC");
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break;
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case 5:
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p += sprintf(p, "Multi-symbol ChipKill ECC");
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break;
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case 6:
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p += sprintf(p, "Master abort");
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break;
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case 7:
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p += sprintf(p, "Target abort");
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break;
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case 8:
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p += sprintf(p, "Parity Error");
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break;
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case 9:
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p += sprintf(p, "Watchdog timeout");
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break;
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case 10:
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p += sprintf(p, "Invalid address");
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break;
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case 11:
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p += sprintf(p, "Mirror Broken");
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break;
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case 12:
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p += sprintf(p, "Memory Sparing");
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break;
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case 13:
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p += sprintf(p, "Scrub corrected error");
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break;
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case 14:
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p += sprintf(p, "Scrub uncorrected error");
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break;
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case 15:
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p += sprintf(p, "Physical Memory Map-out event");
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break;
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default:
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p += sprintf(p, "reserved error (%d)",
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mem_err->error_type);
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}
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} else {
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strcpy(pvt->msg, "unknown error");
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}
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/* Error address */
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if (mem_err->validation_bits & CPER_MEM_VALID_PA) {
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e->page_frame_number = mem_err->physical_addr >> PAGE_SHIFT;
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e->offset_in_page = mem_err->physical_addr & ~PAGE_MASK;
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}
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/* Error grain */
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if (mem_err->validation_bits & CPER_MEM_VALID_PA_MASK)
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e->grain = ~(mem_err->physical_addr_mask & ~PAGE_MASK);
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/* Memory error location, mapped on e->location */
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p = e->location;
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if (mem_err->validation_bits & CPER_MEM_VALID_NODE)
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p += sprintf(p, "node:%d ", mem_err->node);
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if (mem_err->validation_bits & CPER_MEM_VALID_CARD)
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p += sprintf(p, "card:%d ", mem_err->card);
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if (mem_err->validation_bits & CPER_MEM_VALID_MODULE)
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p += sprintf(p, "module:%d ", mem_err->module);
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if (mem_err->validation_bits & CPER_MEM_VALID_RANK_NUMBER)
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p += sprintf(p, "rank:%d ", mem_err->rank);
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if (mem_err->validation_bits & CPER_MEM_VALID_BANK)
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p += sprintf(p, "bank:%d ", mem_err->bank);
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if (mem_err->validation_bits & CPER_MEM_VALID_ROW)
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p += sprintf(p, "row:%d ", mem_err->row);
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if (mem_err->validation_bits & CPER_MEM_VALID_COLUMN)
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p += sprintf(p, "col:%d ", mem_err->column);
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if (mem_err->validation_bits & CPER_MEM_VALID_BIT_POSITION)
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p += sprintf(p, "bit_pos:%d ", mem_err->bit_pos);
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if (mem_err->validation_bits & CPER_MEM_VALID_MODULE_HANDLE) {
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const char *bank = NULL, *device = NULL;
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dmi_memdev_name(mem_err->mem_dev_handle, &bank, &device);
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if (bank != NULL && device != NULL)
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p += sprintf(p, "DIMM location:%s %s ", bank, device);
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else
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p += sprintf(p, "DIMM DMI handle: 0x%.4x ",
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mem_err->mem_dev_handle);
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}
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if (p > e->location)
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*(p - 1) = '\0';
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/* All other fields are mapped on e->other_detail */
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p = pvt->other_detail;
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if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_STATUS) {
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u64 status = mem_err->error_status;
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p += sprintf(p, "status(0x%016llx): ", (long long)status);
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switch ((status >> 8) & 0xff) {
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case 1:
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p += sprintf(p, "Error detected internal to the component ");
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break;
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case 16:
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p += sprintf(p, "Error detected in the bus ");
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break;
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case 4:
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p += sprintf(p, "Storage error in DRAM memory ");
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break;
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case 5:
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p += sprintf(p, "Storage error in TLB ");
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break;
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case 6:
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p += sprintf(p, "Storage error in cache ");
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break;
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case 7:
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p += sprintf(p, "Error in one or more functional units ");
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break;
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case 8:
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p += sprintf(p, "component failed self test ");
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break;
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case 9:
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p += sprintf(p, "Overflow or undervalue of internal queue ");
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break;
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case 17:
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p += sprintf(p, "Virtual address not found on IO-TLB or IO-PDIR ");
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break;
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case 18:
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p += sprintf(p, "Improper access error ");
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break;
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case 19:
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p += sprintf(p, "Access to a memory address which is not mapped to any component ");
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break;
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case 20:
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p += sprintf(p, "Loss of Lockstep ");
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break;
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case 21:
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p += sprintf(p, "Response not associated with a request ");
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break;
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case 22:
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p += sprintf(p, "Bus parity error - must also set the A, C, or D Bits ");
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break;
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case 23:
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p += sprintf(p, "Detection of a PATH_ERROR ");
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break;
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case 25:
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p += sprintf(p, "Bus operation timeout ");
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break;
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case 26:
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p += sprintf(p, "A read was issued to data that has been poisoned ");
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break;
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default:
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p += sprintf(p, "reserved ");
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break;
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}
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}
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if (mem_err->validation_bits & CPER_MEM_VALID_REQUESTOR_ID)
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p += sprintf(p, "requestorID: 0x%016llx ",
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(long long)mem_err->requestor_id);
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if (mem_err->validation_bits & CPER_MEM_VALID_RESPONDER_ID)
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p += sprintf(p, "responderID: 0x%016llx ",
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(long long)mem_err->responder_id);
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if (mem_err->validation_bits & CPER_MEM_VALID_TARGET_ID)
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p += sprintf(p, "targetID: 0x%016llx ",
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(long long)mem_err->responder_id);
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if (p > pvt->other_detail)
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*(p - 1) = '\0';
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/* Generate the trace event */
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grain_bits = fls_long(e->grain);
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snprintf(pvt->detail_location, sizeof(pvt->detail_location),
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"APEI location: %s %s", e->location, e->other_detail);
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trace_mc_event(type, e->msg, e->label, e->error_count,
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mci->mc_idx, e->top_layer, e->mid_layer, e->low_layer,
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(e->page_frame_number << PAGE_SHIFT) | e->offset_in_page,
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grain_bits, e->syndrome, pvt->detail_location);
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edac_raw_mc_handle_error(type, mci, e);
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spin_unlock_irqrestore(&ghes_lock, flags);
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}
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/*
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* Known systems that are safe to enable this module.
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*/
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static struct acpi_platform_list plat_list[] = {
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{"HPE ", "Server ", 0, ACPI_SIG_FADT, all_versions},
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{ } /* End */
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};
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int ghes_edac_register(struct ghes *ghes, struct device *dev)
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{
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bool fake = false;
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int rc, num_dimm = 0;
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struct mem_ctl_info *mci;
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struct edac_mc_layer layers[1];
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struct ghes_edac_dimm_fill dimm_fill;
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int idx;
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/* Check if safe to enable on this system */
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idx = acpi_match_platform_list(plat_list);
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if (!force_load && idx < 0)
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return 0;
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/*
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* We have only one logical memory controller to which all DIMMs belong.
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*/
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if (atomic_inc_return(&ghes_init) > 1)
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return 0;
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/* Get the number of DIMMs */
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dmi_walk(ghes_edac_count_dimms, &num_dimm);
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/* Check if we've got a bogus BIOS */
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if (num_dimm == 0) {
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fake = true;
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num_dimm = 1;
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}
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layers[0].type = EDAC_MC_LAYER_ALL_MEM;
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layers[0].size = num_dimm;
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layers[0].is_virt_csrow = true;
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mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(struct ghes_edac_pvt));
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if (!mci) {
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pr_info("Can't allocate memory for EDAC data\n");
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return -ENOMEM;
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}
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ghes_pvt = mci->pvt_info;
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ghes_pvt->ghes = ghes;
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ghes_pvt->mci = mci;
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|
|
mci->pdev = dev;
|
|
mci->mtype_cap = MEM_FLAG_EMPTY;
|
|
mci->edac_ctl_cap = EDAC_FLAG_NONE;
|
|
mci->edac_cap = EDAC_FLAG_NONE;
|
|
mci->mod_name = "ghes_edac.c";
|
|
mci->ctl_name = "ghes_edac";
|
|
mci->dev_name = "ghes";
|
|
|
|
if (fake) {
|
|
pr_info("This system has a very crappy BIOS: It doesn't even list the DIMMS.\n");
|
|
pr_info("Its SMBIOS info is wrong. It is doubtful that the error report would\n");
|
|
pr_info("work on such system. Use this driver with caution\n");
|
|
} else if (idx < 0) {
|
|
pr_info("This EDAC driver relies on BIOS to enumerate memory and get error reports.\n");
|
|
pr_info("Unfortunately, not all BIOSes reflect the memory layout correctly.\n");
|
|
pr_info("So, the end result of using this driver varies from vendor to vendor.\n");
|
|
pr_info("If you find incorrect reports, please contact your hardware vendor\n");
|
|
pr_info("to correct its BIOS.\n");
|
|
pr_info("This system has %d DIMM sockets.\n", num_dimm);
|
|
}
|
|
|
|
if (!fake) {
|
|
dimm_fill.count = 0;
|
|
dimm_fill.mci = mci;
|
|
dmi_walk(ghes_edac_dmidecode, &dimm_fill);
|
|
} else {
|
|
struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
|
|
mci->n_layers, 0, 0, 0);
|
|
|
|
dimm->nr_pages = 1;
|
|
dimm->grain = 128;
|
|
dimm->mtype = MEM_UNKNOWN;
|
|
dimm->dtype = DEV_UNKNOWN;
|
|
dimm->edac_mode = EDAC_SECDED;
|
|
}
|
|
|
|
rc = edac_mc_add_mc(mci);
|
|
if (rc < 0) {
|
|
pr_info("Can't register at EDAC core\n");
|
|
edac_mc_free(mci);
|
|
return -ENODEV;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
void ghes_edac_unregister(struct ghes *ghes)
|
|
{
|
|
struct mem_ctl_info *mci;
|
|
|
|
mci = ghes_pvt->mci;
|
|
edac_mc_del_mc(mci->pdev);
|
|
edac_mc_free(mci);
|
|
}
|