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![Marc Zyngier](/assets/img/avatar_default.png)
Now that we make sure we don't inject multiple instances of the
same GICv2 SGI at the same time, we've made another bug more
obvious:
If we exit with an active SGI, we completely lose track of which
vcpu it came from. On the next entry, we restore it with 0 as a
source, and if that wasn't the right one, too bad. While this
doesn't seem to trouble GIC-400, the architectural model gets
offended and doesn't deactivate the interrupt on EOI.
Another connected issue is that we will happilly make pending
an interrupt from another vcpu, overriding the above zero with
something that is just as inconsistent. Don't do that.
The final issue is that we signal a maintenance interrupt when
no pending interrupts are present in the LR. Assuming we've fixed
the two issues above, we end-up in a situation where we keep
exiting as soon as we've reached the active state, and not be
able to inject the following pending.
The fix comes in 3 parts:
- GICv2 SGIs have their source vcpu saved if they are active on
exit, and restored on entry
- Multi-SGIs cannot go via the Pending+Active state, as this would
corrupt the source field
- Multi-SGIs are converted to using MI on EOI instead of NPIE
Fixes: 16ca6a607d
("KVM: arm/arm64: vgic: Don't populate multiple LRs with the same vintid")
Reported-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
398 lines
11 KiB
C
398 lines
11 KiB
C
/*
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* Copyright (C) 2015, 2016 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __KVM_ARM_VGIC_H
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#define __KVM_ARM_VGIC_H
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#include <linux/kernel.h>
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#include <linux/kvm.h>
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#include <linux/irqreturn.h>
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#include <linux/spinlock.h>
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#include <linux/static_key.h>
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#include <linux/types.h>
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#include <kvm/iodev.h>
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#include <linux/list.h>
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#include <linux/jump_label.h>
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#include <linux/irqchip/arm-gic-v4.h>
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#define VGIC_V3_MAX_CPUS 255
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#define VGIC_V2_MAX_CPUS 8
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#define VGIC_NR_IRQS_LEGACY 256
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#define VGIC_NR_SGIS 16
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#define VGIC_NR_PPIS 16
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#define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
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#define VGIC_MAX_PRIVATE (VGIC_NR_PRIVATE_IRQS - 1)
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#define VGIC_MAX_SPI 1019
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#define VGIC_MAX_RESERVED 1023
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#define VGIC_MIN_LPI 8192
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#define KVM_IRQCHIP_NUM_PINS (1020 - 32)
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#define irq_is_ppi(irq) ((irq) >= VGIC_NR_SGIS && (irq) < VGIC_NR_PRIVATE_IRQS)
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#define irq_is_spi(irq) ((irq) >= VGIC_NR_PRIVATE_IRQS && \
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(irq) <= VGIC_MAX_SPI)
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enum vgic_type {
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VGIC_V2, /* Good ol' GICv2 */
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VGIC_V3, /* New fancy GICv3 */
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};
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/* same for all guests, as depending only on the _host's_ GIC model */
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struct vgic_global {
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/* type of the host GIC */
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enum vgic_type type;
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/* Physical address of vgic virtual cpu interface */
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phys_addr_t vcpu_base;
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/* GICV mapping, kernel VA */
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void __iomem *vcpu_base_va;
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/* GICV mapping, HYP VA */
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void __iomem *vcpu_hyp_va;
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/* virtual control interface mapping, kernel VA */
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void __iomem *vctrl_base;
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/* virtual control interface mapping, HYP VA */
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void __iomem *vctrl_hyp;
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/* Number of implemented list registers */
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int nr_lr;
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/* Maintenance IRQ number */
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unsigned int maint_irq;
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/* maximum number of VCPUs allowed (GICv2 limits us to 8) */
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int max_gic_vcpus;
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/* Only needed for the legacy KVM_CREATE_IRQCHIP */
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bool can_emulate_gicv2;
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/* Hardware has GICv4? */
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bool has_gicv4;
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/* GIC system register CPU interface */
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struct static_key_false gicv3_cpuif;
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u32 ich_vtr_el2;
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};
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extern struct vgic_global kvm_vgic_global_state;
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#define VGIC_V2_MAX_LRS (1 << 6)
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#define VGIC_V3_MAX_LRS 16
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#define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr)
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enum vgic_irq_config {
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VGIC_CONFIG_EDGE = 0,
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VGIC_CONFIG_LEVEL
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};
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struct vgic_irq {
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spinlock_t irq_lock; /* Protects the content of the struct */
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struct list_head lpi_list; /* Used to link all LPIs together */
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struct list_head ap_list;
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struct kvm_vcpu *vcpu; /* SGIs and PPIs: The VCPU
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* SPIs and LPIs: The VCPU whose ap_list
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* this is queued on.
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*/
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struct kvm_vcpu *target_vcpu; /* The VCPU that this interrupt should
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* be sent to, as a result of the
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* targets reg (v2) or the
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* affinity reg (v3).
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*/
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u32 intid; /* Guest visible INTID */
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bool line_level; /* Level only */
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bool pending_latch; /* The pending latch state used to calculate
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* the pending state for both level
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* and edge triggered IRQs. */
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bool active; /* not used for LPIs */
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bool enabled;
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bool hw; /* Tied to HW IRQ */
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struct kref refcount; /* Used for LPIs */
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u32 hwintid; /* HW INTID number */
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unsigned int host_irq; /* linux irq corresponding to hwintid */
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union {
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u8 targets; /* GICv2 target VCPUs mask */
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u32 mpidr; /* GICv3 target VCPU */
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};
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u8 source; /* GICv2 SGIs only */
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u8 active_source; /* GICv2 SGIs only */
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u8 priority;
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enum vgic_irq_config config; /* Level or edge */
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/*
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* Callback function pointer to in-kernel devices that can tell us the
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* state of the input level of mapped level-triggered IRQ faster than
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* peaking into the physical GIC.
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*
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* Always called in non-preemptible section and the functions can use
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* kvm_arm_get_running_vcpu() to get the vcpu pointer for private
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* IRQs.
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*/
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bool (*get_input_level)(int vintid);
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void *owner; /* Opaque pointer to reserve an interrupt
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for in-kernel devices. */
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};
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struct vgic_register_region;
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struct vgic_its;
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enum iodev_type {
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IODEV_CPUIF,
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IODEV_DIST,
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IODEV_REDIST,
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IODEV_ITS
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};
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struct vgic_io_device {
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gpa_t base_addr;
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union {
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struct kvm_vcpu *redist_vcpu;
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struct vgic_its *its;
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};
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const struct vgic_register_region *regions;
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enum iodev_type iodev_type;
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int nr_regions;
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struct kvm_io_device dev;
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};
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struct vgic_its {
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/* The base address of the ITS control register frame */
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gpa_t vgic_its_base;
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bool enabled;
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struct vgic_io_device iodev;
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struct kvm_device *dev;
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/* These registers correspond to GITS_BASER{0,1} */
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u64 baser_device_table;
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u64 baser_coll_table;
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/* Protects the command queue */
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struct mutex cmd_lock;
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u64 cbaser;
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u32 creadr;
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u32 cwriter;
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/* migration ABI revision in use */
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u32 abi_rev;
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/* Protects the device and collection lists */
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struct mutex its_lock;
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struct list_head device_list;
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struct list_head collection_list;
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};
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struct vgic_state_iter;
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struct vgic_dist {
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bool in_kernel;
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bool ready;
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bool initialized;
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/* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
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u32 vgic_model;
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/* Do injected MSIs require an additional device ID? */
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bool msis_require_devid;
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int nr_spis;
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/* base addresses in guest physical address space: */
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gpa_t vgic_dist_base; /* distributor */
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union {
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/* either a GICv2 CPU interface */
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gpa_t vgic_cpu_base;
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/* or a number of GICv3 redistributor regions */
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struct {
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gpa_t vgic_redist_base;
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gpa_t vgic_redist_free_offset;
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};
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};
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/* distributor enabled */
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bool enabled;
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struct vgic_irq *spis;
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struct vgic_io_device dist_iodev;
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bool has_its;
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/*
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* Contains the attributes and gpa of the LPI configuration table.
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* Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share
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* one address across all redistributors.
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* GICv3 spec: 6.1.2 "LPI Configuration tables"
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*/
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u64 propbaser;
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/* Protects the lpi_list and the count value below. */
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spinlock_t lpi_list_lock;
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struct list_head lpi_list_head;
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int lpi_list_count;
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/* used by vgic-debug */
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struct vgic_state_iter *iter;
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/*
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* GICv4 ITS per-VM data, containing the IRQ domain, the VPE
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* array, the property table pointer as well as allocation
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* data. This essentially ties the Linux IRQ core and ITS
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* together, and avoids leaking KVM's data structures anywhere
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* else.
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*/
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struct its_vm its_vm;
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};
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struct vgic_v2_cpu_if {
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u32 vgic_hcr;
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u32 vgic_vmcr;
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u32 vgic_apr;
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u32 vgic_lr[VGIC_V2_MAX_LRS];
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};
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struct vgic_v3_cpu_if {
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u32 vgic_hcr;
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u32 vgic_vmcr;
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u32 vgic_sre; /* Restored only, change ignored */
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u32 vgic_ap0r[4];
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u32 vgic_ap1r[4];
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u64 vgic_lr[VGIC_V3_MAX_LRS];
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/*
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* GICv4 ITS per-VPE data, containing the doorbell IRQ, the
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* pending table pointer, the its_vm pointer and a few other
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* HW specific things. As for the its_vm structure, this is
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* linking the Linux IRQ subsystem and the ITS together.
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*/
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struct its_vpe its_vpe;
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};
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struct vgic_cpu {
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/* CPU vif control registers for world switch */
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union {
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struct vgic_v2_cpu_if vgic_v2;
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struct vgic_v3_cpu_if vgic_v3;
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};
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unsigned int used_lrs;
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struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS];
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spinlock_t ap_list_lock; /* Protects the ap_list */
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/*
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* List of IRQs that this VCPU should consider because they are either
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* Active or Pending (hence the name; AP list), or because they recently
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* were one of the two and need to be migrated off this list to another
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* VCPU.
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*/
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struct list_head ap_list_head;
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/*
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* Members below are used with GICv3 emulation only and represent
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* parts of the redistributor.
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*/
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struct vgic_io_device rd_iodev;
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struct vgic_io_device sgi_iodev;
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/* Contains the attributes and gpa of the LPI pending tables. */
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u64 pendbaser;
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bool lpis_enabled;
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/* Cache guest priority bits */
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u32 num_pri_bits;
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/* Cache guest interrupt ID bits */
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u32 num_id_bits;
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};
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extern struct static_key_false vgic_v2_cpuif_trap;
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extern struct static_key_false vgic_v3_cpuif_trap;
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int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
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void kvm_vgic_early_init(struct kvm *kvm);
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int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
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int kvm_vgic_create(struct kvm *kvm, u32 type);
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void kvm_vgic_destroy(struct kvm *kvm);
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void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu);
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void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
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int kvm_vgic_map_resources(struct kvm *kvm);
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int kvm_vgic_hyp_init(void);
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void kvm_vgic_init_cpu_hardware(void);
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int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
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bool level, void *owner);
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int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, unsigned int host_irq,
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u32 vintid, bool (*get_input_level)(int vindid));
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int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int vintid);
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bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int vintid);
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int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
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void kvm_vgic_load(struct kvm_vcpu *vcpu);
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void kvm_vgic_put(struct kvm_vcpu *vcpu);
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#define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel))
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#define vgic_initialized(k) ((k)->arch.vgic.initialized)
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#define vgic_ready(k) ((k)->arch.vgic.ready)
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#define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \
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((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))
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bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
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void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
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void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
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void kvm_vgic_reset_mapped_irq(struct kvm_vcpu *vcpu, u32 vintid);
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void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
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/**
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* kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
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*
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* The host's GIC naturally limits the maximum amount of VCPUs a guest
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* can use.
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*/
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static inline int kvm_vgic_get_max_vcpus(void)
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{
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return kvm_vgic_global_state.max_gic_vcpus;
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}
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int kvm_send_userspace_msi(struct kvm *kvm, struct kvm_msi *msi);
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/**
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* kvm_vgic_setup_default_irq_routing:
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* Setup a default flat gsi routing table mapping all SPIs
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*/
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int kvm_vgic_setup_default_irq_routing(struct kvm *kvm);
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int kvm_vgic_set_owner(struct kvm_vcpu *vcpu, unsigned int intid, void *owner);
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struct kvm_kernel_irq_routing_entry;
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int kvm_vgic_v4_set_forwarding(struct kvm *kvm, int irq,
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struct kvm_kernel_irq_routing_entry *irq_entry);
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int kvm_vgic_v4_unset_forwarding(struct kvm *kvm, int irq,
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struct kvm_kernel_irq_routing_entry *irq_entry);
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void kvm_vgic_v4_enable_doorbell(struct kvm_vcpu *vcpu);
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void kvm_vgic_v4_disable_doorbell(struct kvm_vcpu *vcpu);
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#endif /* __KVM_ARM_VGIC_H */
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