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![Oren Weil](/assets/img/avatar_default.png)
define the MEI protocol msg structs and HW registers, also define the MEI internal status and struct Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Itzhak Tzeel-Krupp <itzhak.tzeel-krupp@intel.com> Signed-off-by: Oren Weil <oren.jer.weil@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
333 lines
8.3 KiB
C
333 lines
8.3 KiB
C
/*
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*
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* Intel Management Engine Interface (Intel MEI) Linux driver
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* Copyright (c) 2003-2011, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#ifndef _MEI_HW_TYPES_H_
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#define _MEI_HW_TYPES_H_
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#include <linux/uuid.h>
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/*
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* Timeouts
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*/
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#define MEI_INTEROP_TIMEOUT (HZ * 7)
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#define MEI_CONNECT_TIMEOUT 3 /* at least 2 seconds */
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#define CONNECT_TIMEOUT 15 /* HPS definition */
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#define INIT_CLIENTS_TIMEOUT 15 /* HPS definition */
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#define IAMTHIF_STALL_TIMER 12 /* seconds */
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#define IAMTHIF_READ_TIMER 10000 /* ms */
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/*
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* Internal Clients Number
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*/
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#define MEI_WD_HOST_CLIENT_ID 1
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#define MEI_IAMTHIF_HOST_CLIENT_ID 2
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/*
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* MEI device IDs
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*/
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#define MEI_DEV_ID_82946GZ 0x2974 /* 82946GZ/GL */
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#define MEI_DEV_ID_82G35 0x2984 /* 82G35 Express */
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#define MEI_DEV_ID_82Q965 0x2994 /* 82Q963/Q965 */
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#define MEI_DEV_ID_82G965 0x29A4 /* 82P965/G965 */
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#define MEI_DEV_ID_82GM965 0x2A04 /* Mobile PM965/GM965 */
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#define MEI_DEV_ID_82GME965 0x2A14 /* Mobile GME965/GLE960 */
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#define MEI_DEV_ID_ICH9_82Q35 0x29B4 /* 82Q35 Express */
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#define MEI_DEV_ID_ICH9_82G33 0x29C4 /* 82G33/G31/P35/P31 Express */
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#define MEI_DEV_ID_ICH9_82Q33 0x29D4 /* 82Q33 Express */
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#define MEI_DEV_ID_ICH9_82X38 0x29E4 /* 82X38/X48 Express */
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#define MEI_DEV_ID_ICH9_3200 0x29F4 /* 3200/3210 Server */
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#define MEI_DEV_ID_ICH9_6 0x28B4 /* Bearlake */
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#define MEI_DEV_ID_ICH9_7 0x28C4 /* Bearlake */
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#define MEI_DEV_ID_ICH9_8 0x28D4 /* Bearlake */
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#define MEI_DEV_ID_ICH9_9 0x28E4 /* Bearlake */
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#define MEI_DEV_ID_ICH9_10 0x28F4 /* Bearlake */
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#define MEI_DEV_ID_ICH9M_1 0x2A44 /* Cantiga */
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#define MEI_DEV_ID_ICH9M_2 0x2A54 /* Cantiga */
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#define MEI_DEV_ID_ICH9M_3 0x2A64 /* Cantiga */
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#define MEI_DEV_ID_ICH9M_4 0x2A74 /* Cantiga */
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#define MEI_DEV_ID_ICH10_1 0x2E04 /* Eaglelake */
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#define MEI_DEV_ID_ICH10_2 0x2E14 /* Eaglelake */
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#define MEI_DEV_ID_ICH10_3 0x2E24 /* Eaglelake */
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#define MEI_DEV_ID_ICH10_4 0x2E34 /* Eaglelake */
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#define MEI_DEV_ID_IBXPK_1 0x3B64 /* Calpella */
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#define MEI_DEV_ID_IBXPK_2 0x3B65 /* Calpella */
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#define MEI_DEV_ID_CPT_1 0x1C3A /* Cougerpoint */
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#define MEI_DEV_ID_PBG_1 0x1D3A /* PBG */
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#define MEI_DEV_ID_PPT_1 0x1E3A /* Pantherpoint PPT */
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#define MEI_DEV_ID_PPT_2 0x1CBA /* Pantherpoint PPT */
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#define MEI_DEV_ID_PPT_3 0x1DBA /* Pantherpoint PPT */
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/*
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* MEI HW Section
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*/
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/* MEI registers */
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/* H_CB_WW - Host Circular Buffer (CB) Write Window register */
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#define H_CB_WW 0
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/* H_CSR - Host Control Status register */
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#define H_CSR 4
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/* ME_CB_RW - ME Circular Buffer Read Window register (read only) */
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#define ME_CB_RW 8
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/* ME_CSR_HA - ME Control Status Host Access register (read only) */
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#define ME_CSR_HA 0xC
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/* register bits of H_CSR (Host Control Status register) */
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/* Host Circular Buffer Depth - maximum number of 32-bit entries in CB */
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#define H_CBD 0xFF000000
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/* Host Circular Buffer Write Pointer */
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#define H_CBWP 0x00FF0000
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/* Host Circular Buffer Read Pointer */
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#define H_CBRP 0x0000FF00
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/* Host Reset */
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#define H_RST 0x00000010
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/* Host Ready */
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#define H_RDY 0x00000008
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/* Host Interrupt Generate */
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#define H_IG 0x00000004
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/* Host Interrupt Status */
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#define H_IS 0x00000002
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/* Host Interrupt Enable */
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#define H_IE 0x00000001
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/* register bits of ME_CSR_HA (ME Control Status Host Access register) */
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/* ME CB (Circular Buffer) Depth HRA (Host Read Access) - host read only
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access to ME_CBD */
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#define ME_CBD_HRA 0xFF000000
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/* ME CB Write Pointer HRA - host read only access to ME_CBWP */
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#define ME_CBWP_HRA 0x00FF0000
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/* ME CB Read Pointer HRA - host read only access to ME_CBRP */
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#define ME_CBRP_HRA 0x0000FF00
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/* ME Reset HRA - host read only access to ME_RST */
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#define ME_RST_HRA 0x00000010
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/* ME Ready HRA - host read only access to ME_RDY */
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#define ME_RDY_HRA 0x00000008
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/* ME Interrupt Generate HRA - host read only access to ME_IG */
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#define ME_IG_HRA 0x00000004
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/* ME Interrupt Status HRA - host read only access to ME_IS */
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#define ME_IS_HRA 0x00000002
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/* ME Interrupt Enable HRA - host read only access to ME_IE */
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#define ME_IE_HRA 0x00000001
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/*
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* MEI Version
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*/
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#define HBM_MINOR_VERSION 0
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#define HBM_MAJOR_VERSION 1
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#define HBM_TIMEOUT 1 /* 1 second */
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/*
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* MEI Bus Message Command IDs
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*/
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#define HOST_START_REQ_CMD 0x01
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#define HOST_START_RES_CMD 0x81
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#define HOST_STOP_REQ_CMD 0x02
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#define HOST_STOP_RES_CMD 0x82
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#define ME_STOP_REQ_CMD 0x03
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#define HOST_ENUM_REQ_CMD 0x04
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#define HOST_ENUM_RES_CMD 0x84
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#define HOST_CLIENT_PROPERTIES_REQ_CMD 0x05
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#define HOST_CLIENT_PROPERTIES_RES_CMD 0x85
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#define CLIENT_CONNECT_REQ_CMD 0x06
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#define CLIENT_CONNECT_RES_CMD 0x86
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#define CLIENT_DISCONNECT_REQ_CMD 0x07
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#define CLIENT_DISCONNECT_RES_CMD 0x87
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#define MEI_FLOW_CONTROL_CMD 0x08
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/*
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* MEI Stop Reason
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* used by hbm_host_stop_request.reason
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*/
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enum mei_stop_reason_types {
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DRIVER_STOP_REQUEST = 0x00,
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DEVICE_D1_ENTRY = 0x01,
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DEVICE_D2_ENTRY = 0x02,
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DEVICE_D3_ENTRY = 0x03,
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SYSTEM_S1_ENTRY = 0x04,
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SYSTEM_S2_ENTRY = 0x05,
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SYSTEM_S3_ENTRY = 0x06,
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SYSTEM_S4_ENTRY = 0x07,
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SYSTEM_S5_ENTRY = 0x08
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};
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/*
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* Client Connect Status
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* used by hbm_client_connect_response.status
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*/
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enum client_connect_status_types {
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CCS_SUCCESS = 0x00,
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CCS_NOT_FOUND = 0x01,
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CCS_ALREADY_STARTED = 0x02,
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CCS_OUT_OF_RESOURCES = 0x03,
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CCS_MESSAGE_SMALL = 0x04
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};
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/*
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* Client Disconnect Status
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*/
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enum client_disconnect_status_types {
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CDS_SUCCESS = 0x00
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};
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/*
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* MEI BUS Interface Section
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*/
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struct mei_msg_hdr {
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u32 me_addr:8;
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u32 host_addr:8;
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u32 length:9;
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u32 reserved:6;
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u32 msg_complete:1;
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} __packed;
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struct hbm_cmd {
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u8 cmd:7;
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u8 is_response:1;
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} __packed;
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struct mei_bus_message {
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struct hbm_cmd cmd;
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u8 command_specific_data[];
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} __packed;
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struct hbm_version {
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u8 minor_version;
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u8 major_version;
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} __packed;
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struct hbm_host_version_request {
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struct hbm_cmd cmd;
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u8 reserved;
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struct hbm_version host_version;
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} __packed;
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struct hbm_host_version_response {
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struct hbm_cmd cmd;
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int host_version_supported;
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struct hbm_version me_max_version;
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} __packed;
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struct hbm_host_stop_request {
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struct hbm_cmd cmd;
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u8 reason;
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u8 reserved[2];
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} __packed;
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struct hbm_host_stop_response {
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struct hbm_cmd cmd;
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u8 reserved[3];
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} __packed;
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struct hbm_me_stop_request {
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struct hbm_cmd cmd;
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u8 reason;
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u8 reserved[2];
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} __packed;
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struct hbm_host_enum_request {
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struct hbm_cmd cmd;
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u8 reserved[3];
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} __packed;
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struct hbm_host_enum_response {
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struct hbm_cmd cmd;
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u8 reserved[3];
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u8 valid_addresses[32];
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} __packed;
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struct mei_client_properties {
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uuid_le protocol_name;
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u8 protocol_version;
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u8 max_number_of_connections;
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u8 fixed_address;
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u8 single_recv_buf;
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u32 max_msg_length;
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} __packed;
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struct hbm_props_request {
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struct hbm_cmd cmd;
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u8 address;
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u8 reserved[2];
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} __packed;
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struct hbm_props_response {
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struct hbm_cmd cmd;
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u8 address;
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u8 status;
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u8 reserved[1];
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struct mei_client_properties client_properties;
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} __packed;
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struct hbm_client_connect_request {
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struct hbm_cmd cmd;
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u8 me_addr;
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u8 host_addr;
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u8 reserved;
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} __packed;
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struct hbm_client_connect_response {
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struct hbm_cmd cmd;
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u8 me_addr;
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u8 host_addr;
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u8 status;
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} __packed;
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struct hbm_client_disconnect_request {
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struct hbm_cmd cmd;
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u8 me_addr;
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u8 host_addr;
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u8 reserved[1];
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} __packed;
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#define MEI_FC_MESSAGE_RESERVED_LENGTH 5
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struct hbm_flow_control {
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struct hbm_cmd cmd;
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u8 me_addr;
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u8 host_addr;
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u8 reserved[MEI_FC_MESSAGE_RESERVED_LENGTH];
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} __packed;
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struct mei_me_client {
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struct mei_client_properties props;
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u8 client_id;
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u8 mei_flow_ctrl_creds;
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} __packed;
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#endif
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