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![Bernhard Walle](/assets/img/avatar_default.png)
Remove functions and definitions that refer to USB since the driver doesn't support USB and it's not planned to add USB support to that driver. So the code is just dead code which can be removed. Cc: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Bernhard Walle <walle@corscience.de> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
695 lines
21 KiB
C
695 lines
21 KiB
C
/***********************license start***************
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* Author: Cavium Networks
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*
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2008 Cavium Networks
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this file; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* or visit http://www.gnu.org/licenses/.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium Networks for more information
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***********************license end**************************************/
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/*
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*
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* Helper functions to abstract board specific data about
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* network ports from the rest of the cvmx-helper files.
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*/
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#include <asm/octeon/octeon.h>
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#include <asm/octeon/cvmx-bootinfo.h>
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#include "cvmx-config.h"
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#include "cvmx-mdio.h"
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#include "cvmx-helper.h"
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#include "cvmx-helper-util.h"
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#include "cvmx-helper-board.h"
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#include "cvmx-gmxx-defs.h"
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#include "cvmx-asxx-defs.h"
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/**
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* cvmx_override_board_link_get(int ipd_port) is a function
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* pointer. It is meant to allow customization of the process of
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* talking to a PHY to determine link speed. It is called every
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* time a PHY must be polled for link status. Users should set
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* this pointer to a function before calling any cvmx-helper
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* operations.
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*/
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cvmx_helper_link_info_t(*cvmx_override_board_link_get) (int ipd_port) =
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NULL;
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/**
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* Return the MII PHY address associated with the given IPD
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* port. A result of -1 means there isn't a MII capable PHY
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* connected to this port. On chips supporting multiple MII
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* busses the bus number is encoded in bits <15:8>.
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*
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* This function must be modified for every new Octeon board.
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* Internally it uses switch statements based on the cvmx_sysinfo
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* data to determine board types and revisions. It replies on the
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* fact that every Octeon board receives a unique board type
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* enumeration from the bootloader.
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*
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* @ipd_port: Octeon IPD port to get the MII address for.
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*
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* Returns MII PHY address and bus number or -1.
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*/
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int cvmx_helper_board_get_mii_address(int ipd_port)
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{
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switch (cvmx_sysinfo_get()->board_type) {
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case CVMX_BOARD_TYPE_SIM:
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/* Simulator doesn't have MII */
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return -1;
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case CVMX_BOARD_TYPE_EBT3000:
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case CVMX_BOARD_TYPE_EBT5800:
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case CVMX_BOARD_TYPE_THUNDER:
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case CVMX_BOARD_TYPE_NICPRO2:
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/* Interface 0 is SPI4, interface 1 is RGMII */
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if ((ipd_port >= 16) && (ipd_port < 20))
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return ipd_port - 16;
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else
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return -1;
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case CVMX_BOARD_TYPE_KODAMA:
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case CVMX_BOARD_TYPE_EBH3100:
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case CVMX_BOARD_TYPE_HIKARI:
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case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
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case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
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case CVMX_BOARD_TYPE_CN3020_EVB_HS5:
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/*
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* Port 0 is WAN connected to a PHY, Port 1 is GMII
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* connected to a switch
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*/
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if (ipd_port == 0)
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return 4;
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else if (ipd_port == 1)
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return 9;
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else
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return -1;
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case CVMX_BOARD_TYPE_NAC38:
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/* Board has 8 RGMII ports PHYs are 0-7 */
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if ((ipd_port >= 0) && (ipd_port < 4))
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return ipd_port;
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else if ((ipd_port >= 16) && (ipd_port < 20))
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return ipd_port - 16 + 4;
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else
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return -1;
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case CVMX_BOARD_TYPE_EBH3000:
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/* Board has dual SPI4 and no PHYs */
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return -1;
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case CVMX_BOARD_TYPE_EBH5200:
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case CVMX_BOARD_TYPE_EBH5201:
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case CVMX_BOARD_TYPE_EBT5200:
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/*
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* Board has 4 SGMII ports. The PHYs start right after the MII
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* ports MII0 = 0, MII1 = 1, SGMII = 2-5.
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*/
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if ((ipd_port >= 0) && (ipd_port < 4))
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return ipd_port + 2;
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else
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return -1;
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case CVMX_BOARD_TYPE_EBH5600:
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case CVMX_BOARD_TYPE_EBH5601:
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case CVMX_BOARD_TYPE_EBH5610:
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/*
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* Board has 8 SGMII ports. 4 connect out, two connect
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* to a switch, and 2 loop to each other
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*/
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if ((ipd_port >= 0) && (ipd_port < 4))
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return ipd_port + 1;
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else
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return -1;
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case CVMX_BOARD_TYPE_CUST_NB5:
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if (ipd_port == 2)
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return 4;
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else
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return -1;
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case CVMX_BOARD_TYPE_NIC_XLE_4G:
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/* Board has 4 SGMII ports. connected QLM3(interface 1) */
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if ((ipd_port >= 16) && (ipd_port < 20))
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return ipd_port - 16 + 1;
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else
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return -1;
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case CVMX_BOARD_TYPE_BBGW_REF:
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/*
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* No PHYs are connected to Octeon, everything is
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* through switch.
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*/
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return -1;
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case CVMX_BOARD_TYPE_CUST_WSX16:
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if (ipd_port >= 0 && ipd_port <= 3)
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return ipd_port;
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else if (ipd_port >= 16 && ipd_port <= 19)
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return ipd_port - 16 + 4;
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else
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return -1;
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}
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/* Some unknown board. Somebody forgot to update this function... */
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cvmx_dprintf
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("cvmx_helper_board_get_mii_address: Unknown board type %d\n",
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cvmx_sysinfo_get()->board_type);
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return -1;
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}
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/**
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* This function is the board specific method of determining an
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* ethernet ports link speed. Most Octeon boards have Marvell PHYs
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* and are handled by the fall through case. This function must be
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* updated for boards that don't have the normal Marvell PHYs.
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*
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* This function must be modified for every new Octeon board.
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* Internally it uses switch statements based on the cvmx_sysinfo
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* data to determine board types and revisions. It relies on the
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* fact that every Octeon board receives a unique board type
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* enumeration from the bootloader.
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*
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* @ipd_port: IPD input port associated with the port we want to get link
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* status for.
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*
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* Returns The ports link status. If the link isn't fully resolved, this must
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* return zero.
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*/
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cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
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{
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cvmx_helper_link_info_t result;
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int phy_addr;
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int is_broadcom_phy = 0;
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/* Give the user a chance to override the processing of this function */
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if (cvmx_override_board_link_get)
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return cvmx_override_board_link_get(ipd_port);
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/* Unless we fix it later, all links are defaulted to down */
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result.u64 = 0;
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/*
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* This switch statement should handle all ports that either don't use
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* Marvell PHYS, or don't support in-band status.
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*/
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switch (cvmx_sysinfo_get()->board_type) {
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case CVMX_BOARD_TYPE_SIM:
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/* The simulator gives you a simulated 1Gbps full duplex link */
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result.s.link_up = 1;
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result.s.full_duplex = 1;
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result.s.speed = 1000;
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return result;
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case CVMX_BOARD_TYPE_EBH3100:
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case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
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case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
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case CVMX_BOARD_TYPE_CN3020_EVB_HS5:
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/* Port 1 on these boards is always Gigabit */
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if (ipd_port == 1) {
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result.s.link_up = 1;
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result.s.full_duplex = 1;
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result.s.speed = 1000;
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return result;
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}
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/* Fall through to the generic code below */
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break;
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case CVMX_BOARD_TYPE_CUST_NB5:
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/* Port 1 on these boards is always Gigabit */
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if (ipd_port == 1) {
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result.s.link_up = 1;
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result.s.full_duplex = 1;
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result.s.speed = 1000;
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return result;
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} else /* The other port uses a broadcom PHY */
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is_broadcom_phy = 1;
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break;
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case CVMX_BOARD_TYPE_BBGW_REF:
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/* Port 1 on these boards is always Gigabit */
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if (ipd_port == 2) {
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/* Port 2 is not hooked up */
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result.u64 = 0;
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return result;
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} else {
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/* Ports 0 and 1 connect to the switch */
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result.s.link_up = 1;
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result.s.full_duplex = 1;
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result.s.speed = 1000;
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return result;
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}
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break;
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}
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phy_addr = cvmx_helper_board_get_mii_address(ipd_port);
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if (phy_addr != -1) {
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if (is_broadcom_phy) {
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/*
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* Below we are going to read SMI/MDIO
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* register 0x19 which works on Broadcom
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* parts
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*/
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int phy_status =
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cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
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0x19);
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switch ((phy_status >> 8) & 0x7) {
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case 0:
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result.u64 = 0;
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break;
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case 1:
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result.s.link_up = 1;
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result.s.full_duplex = 0;
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result.s.speed = 10;
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break;
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case 2:
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result.s.link_up = 1;
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result.s.full_duplex = 1;
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result.s.speed = 10;
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break;
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case 3:
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result.s.link_up = 1;
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result.s.full_duplex = 0;
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result.s.speed = 100;
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break;
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case 4:
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result.s.link_up = 1;
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result.s.full_duplex = 1;
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result.s.speed = 100;
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break;
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case 5:
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result.s.link_up = 1;
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result.s.full_duplex = 1;
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result.s.speed = 100;
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break;
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case 6:
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result.s.link_up = 1;
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result.s.full_duplex = 0;
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result.s.speed = 1000;
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break;
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case 7:
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result.s.link_up = 1;
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result.s.full_duplex = 1;
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result.s.speed = 1000;
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break;
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}
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} else {
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/*
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* This code assumes we are using a Marvell
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* Gigabit PHY. All the speed information can
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* be read from register 17 in one
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* go. Somebody using a different PHY will
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* need to handle it above in the board
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* specific area.
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*/
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int phy_status =
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cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 17);
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/*
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* If the resolve bit 11 isn't set, see if
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* autoneg is turned off (bit 12, reg 0). The
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* resolve bit doesn't get set properly when
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* autoneg is off, so force it.
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*/
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if ((phy_status & (1 << 11)) == 0) {
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int auto_status =
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cvmx_mdio_read(phy_addr >> 8,
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phy_addr & 0xff, 0);
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if ((auto_status & (1 << 12)) == 0)
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phy_status |= 1 << 11;
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}
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/*
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* Only return a link if the PHY has finished
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* auto negotiation and set the resolved bit
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* (bit 11)
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*/
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if (phy_status & (1 << 11)) {
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result.s.link_up = 1;
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result.s.full_duplex = ((phy_status >> 13) & 1);
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switch ((phy_status >> 14) & 3) {
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case 0: /* 10 Mbps */
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result.s.speed = 10;
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break;
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case 1: /* 100 Mbps */
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result.s.speed = 100;
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break;
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case 2: /* 1 Gbps */
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result.s.speed = 1000;
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break;
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case 3: /* Illegal */
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result.u64 = 0;
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break;
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}
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}
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}
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} else if (OCTEON_IS_MODEL(OCTEON_CN3XXX)
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|| OCTEON_IS_MODEL(OCTEON_CN58XX)
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|| OCTEON_IS_MODEL(OCTEON_CN50XX)) {
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/*
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* We don't have a PHY address, so attempt to use
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* in-band status. It is really important that boards
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* not supporting in-band status never get
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* here. Reading broken in-band status tends to do bad
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* things
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*/
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union cvmx_gmxx_rxx_rx_inbnd inband_status;
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int interface = cvmx_helper_get_interface_num(ipd_port);
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int index = cvmx_helper_get_interface_index_num(ipd_port);
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inband_status.u64 =
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cvmx_read_csr(CVMX_GMXX_RXX_RX_INBND(index, interface));
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result.s.link_up = inband_status.s.status;
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result.s.full_duplex = inband_status.s.duplex;
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switch (inband_status.s.speed) {
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case 0: /* 10 Mbps */
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result.s.speed = 10;
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break;
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case 1: /* 100 Mbps */
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result.s.speed = 100;
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break;
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case 2: /* 1 Gbps */
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result.s.speed = 1000;
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break;
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case 3: /* Illegal */
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result.u64 = 0;
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break;
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}
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} else {
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/*
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* We don't have a PHY address and we don't have
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* in-band status. There is no way to determine the
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* link speed. Return down assuming this port isn't
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* wired
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*/
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result.u64 = 0;
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}
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/* If link is down, return all fields as zero. */
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if (!result.s.link_up)
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result.u64 = 0;
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return result;
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}
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/**
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* This function as a board specific method of changing the PHY
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* speed, duplex, and auto-negotiation. This programs the PHY and
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* not Octeon. This can be used to force Octeon's links to
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* specific settings.
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*
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* @phy_addr: The address of the PHY to program
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* @enable_autoneg:
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* Non zero if you want to enable auto-negotiation.
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* @link_info: Link speed to program. If the speed is zero and auto-negotiation
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* is enabled, all possible negotiation speeds are advertised.
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*
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* Returns Zero on success, negative on failure
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*/
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int cvmx_helper_board_link_set_phy(int phy_addr,
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cvmx_helper_board_set_phy_link_flags_types_t
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link_flags,
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cvmx_helper_link_info_t link_info)
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{
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/* Set the flow control settings based on link_flags */
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if ((link_flags & set_phy_link_flags_flow_control_mask) !=
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set_phy_link_flags_flow_control_dont_touch) {
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cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver;
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reg_autoneg_adver.u16 =
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cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
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CVMX_MDIO_PHY_REG_AUTONEG_ADVER);
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reg_autoneg_adver.s.asymmetric_pause =
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(link_flags & set_phy_link_flags_flow_control_mask) ==
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set_phy_link_flags_flow_control_enable;
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reg_autoneg_adver.s.pause =
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(link_flags & set_phy_link_flags_flow_control_mask) ==
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set_phy_link_flags_flow_control_enable;
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cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
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CVMX_MDIO_PHY_REG_AUTONEG_ADVER,
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reg_autoneg_adver.u16);
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}
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/* If speed isn't set and autoneg is on advertise all supported modes */
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if ((link_flags & set_phy_link_flags_autoneg)
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&& (link_info.s.speed == 0)) {
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cvmx_mdio_phy_reg_control_t reg_control;
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cvmx_mdio_phy_reg_status_t reg_status;
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cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver;
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cvmx_mdio_phy_reg_extended_status_t reg_extended_status;
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cvmx_mdio_phy_reg_control_1000_t reg_control_1000;
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reg_status.u16 =
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cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
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CVMX_MDIO_PHY_REG_STATUS);
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reg_autoneg_adver.u16 =
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cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
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CVMX_MDIO_PHY_REG_AUTONEG_ADVER);
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reg_autoneg_adver.s.advert_100base_t4 =
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reg_status.s.capable_100base_t4;
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reg_autoneg_adver.s.advert_10base_tx_full =
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reg_status.s.capable_10_full;
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reg_autoneg_adver.s.advert_10base_tx_half =
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reg_status.s.capable_10_half;
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reg_autoneg_adver.s.advert_100base_tx_full =
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reg_status.s.capable_100base_x_full;
|
|
reg_autoneg_adver.s.advert_100base_tx_half =
|
|
reg_status.s.capable_100base_x_half;
|
|
cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
|
|
CVMX_MDIO_PHY_REG_AUTONEG_ADVER,
|
|
reg_autoneg_adver.u16);
|
|
if (reg_status.s.capable_extended_status) {
|
|
reg_extended_status.u16 =
|
|
cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
|
|
CVMX_MDIO_PHY_REG_EXTENDED_STATUS);
|
|
reg_control_1000.u16 =
|
|
cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
|
|
CVMX_MDIO_PHY_REG_CONTROL_1000);
|
|
reg_control_1000.s.advert_1000base_t_full =
|
|
reg_extended_status.s.capable_1000base_t_full;
|
|
reg_control_1000.s.advert_1000base_t_half =
|
|
reg_extended_status.s.capable_1000base_t_half;
|
|
cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
|
|
CVMX_MDIO_PHY_REG_CONTROL_1000,
|
|
reg_control_1000.u16);
|
|
}
|
|
reg_control.u16 =
|
|
cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
|
|
CVMX_MDIO_PHY_REG_CONTROL);
|
|
reg_control.s.autoneg_enable = 1;
|
|
reg_control.s.restart_autoneg = 1;
|
|
cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
|
|
CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16);
|
|
} else if ((link_flags & set_phy_link_flags_autoneg)) {
|
|
cvmx_mdio_phy_reg_control_t reg_control;
|
|
cvmx_mdio_phy_reg_status_t reg_status;
|
|
cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver;
|
|
cvmx_mdio_phy_reg_extended_status_t reg_extended_status;
|
|
cvmx_mdio_phy_reg_control_1000_t reg_control_1000;
|
|
|
|
reg_status.u16 =
|
|
cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
|
|
CVMX_MDIO_PHY_REG_STATUS);
|
|
reg_autoneg_adver.u16 =
|
|
cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
|
|
CVMX_MDIO_PHY_REG_AUTONEG_ADVER);
|
|
reg_autoneg_adver.s.advert_100base_t4 = 0;
|
|
reg_autoneg_adver.s.advert_10base_tx_full = 0;
|
|
reg_autoneg_adver.s.advert_10base_tx_half = 0;
|
|
reg_autoneg_adver.s.advert_100base_tx_full = 0;
|
|
reg_autoneg_adver.s.advert_100base_tx_half = 0;
|
|
if (reg_status.s.capable_extended_status) {
|
|
reg_extended_status.u16 =
|
|
cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
|
|
CVMX_MDIO_PHY_REG_EXTENDED_STATUS);
|
|
reg_control_1000.u16 =
|
|
cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
|
|
CVMX_MDIO_PHY_REG_CONTROL_1000);
|
|
reg_control_1000.s.advert_1000base_t_full = 0;
|
|
reg_control_1000.s.advert_1000base_t_half = 0;
|
|
}
|
|
switch (link_info.s.speed) {
|
|
case 10:
|
|
reg_autoneg_adver.s.advert_10base_tx_full =
|
|
link_info.s.full_duplex;
|
|
reg_autoneg_adver.s.advert_10base_tx_half =
|
|
!link_info.s.full_duplex;
|
|
break;
|
|
case 100:
|
|
reg_autoneg_adver.s.advert_100base_tx_full =
|
|
link_info.s.full_duplex;
|
|
reg_autoneg_adver.s.advert_100base_tx_half =
|
|
!link_info.s.full_duplex;
|
|
break;
|
|
case 1000:
|
|
reg_control_1000.s.advert_1000base_t_full =
|
|
link_info.s.full_duplex;
|
|
reg_control_1000.s.advert_1000base_t_half =
|
|
!link_info.s.full_duplex;
|
|
break;
|
|
}
|
|
cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
|
|
CVMX_MDIO_PHY_REG_AUTONEG_ADVER,
|
|
reg_autoneg_adver.u16);
|
|
if (reg_status.s.capable_extended_status)
|
|
cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
|
|
CVMX_MDIO_PHY_REG_CONTROL_1000,
|
|
reg_control_1000.u16);
|
|
reg_control.u16 =
|
|
cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
|
|
CVMX_MDIO_PHY_REG_CONTROL);
|
|
reg_control.s.autoneg_enable = 1;
|
|
reg_control.s.restart_autoneg = 1;
|
|
cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
|
|
CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16);
|
|
} else {
|
|
cvmx_mdio_phy_reg_control_t reg_control;
|
|
reg_control.u16 =
|
|
cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
|
|
CVMX_MDIO_PHY_REG_CONTROL);
|
|
reg_control.s.autoneg_enable = 0;
|
|
reg_control.s.restart_autoneg = 1;
|
|
reg_control.s.duplex = link_info.s.full_duplex;
|
|
if (link_info.s.speed == 1000) {
|
|
reg_control.s.speed_msb = 1;
|
|
reg_control.s.speed_lsb = 0;
|
|
} else if (link_info.s.speed == 100) {
|
|
reg_control.s.speed_msb = 0;
|
|
reg_control.s.speed_lsb = 1;
|
|
} else if (link_info.s.speed == 10) {
|
|
reg_control.s.speed_msb = 0;
|
|
reg_control.s.speed_lsb = 0;
|
|
}
|
|
cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
|
|
CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* This function is called by cvmx_helper_interface_probe() after it
|
|
* determines the number of ports Octeon can support on a specific
|
|
* interface. This function is the per board location to override
|
|
* this value. It is called with the number of ports Octeon might
|
|
* support and should return the number of actual ports on the
|
|
* board.
|
|
*
|
|
* This function must be modifed for every new Octeon board.
|
|
* Internally it uses switch statements based on the cvmx_sysinfo
|
|
* data to determine board types and revisions. It relys on the
|
|
* fact that every Octeon board receives a unique board type
|
|
* enumeration from the bootloader.
|
|
*
|
|
* @interface: Interface to probe
|
|
* @supported_ports:
|
|
* Number of ports Octeon supports.
|
|
*
|
|
* Returns Number of ports the actual board supports. Many times this will
|
|
* simple be "support_ports".
|
|
*/
|
|
int __cvmx_helper_board_interface_probe(int interface, int supported_ports)
|
|
{
|
|
switch (cvmx_sysinfo_get()->board_type) {
|
|
case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
|
|
if (interface == 0)
|
|
return 2;
|
|
break;
|
|
case CVMX_BOARD_TYPE_BBGW_REF:
|
|
if (interface == 0)
|
|
return 2;
|
|
break;
|
|
case CVMX_BOARD_TYPE_NIC_XLE_4G:
|
|
if (interface == 0)
|
|
return 0;
|
|
break;
|
|
/* The 2nd interface on the EBH5600 is connected to the Marvel switch,
|
|
which we don't support. Disable ports connected to it */
|
|
case CVMX_BOARD_TYPE_EBH5600:
|
|
if (interface == 1)
|
|
return 0;
|
|
break;
|
|
}
|
|
return supported_ports;
|
|
}
|
|
|
|
/**
|
|
* Enable packet input/output from the hardware. This function is
|
|
* called after by cvmx_helper_packet_hardware_enable() to
|
|
* perform board specific initialization. For most boards
|
|
* nothing is needed.
|
|
*
|
|
* @interface: Interface to enable
|
|
*
|
|
* Returns Zero on success, negative on failure
|
|
*/
|
|
int __cvmx_helper_board_hardware_enable(int interface)
|
|
{
|
|
if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CN3005_EVB_HS5) {
|
|
if (interface == 0) {
|
|
/* Different config for switch port */
|
|
cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(1, interface), 0);
|
|
cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(1, interface), 0);
|
|
/*
|
|
* Boards with gigabit WAN ports need a
|
|
* different setting that is compatible with
|
|
* 100 Mbit settings
|
|
*/
|
|
cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface),
|
|
0xc);
|
|
cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface),
|
|
0xc);
|
|
}
|
|
} else if (cvmx_sysinfo_get()->board_type ==
|
|
CVMX_BOARD_TYPE_CN3010_EVB_HS5) {
|
|
/*
|
|
* Broadcom PHYs require differnet ASX
|
|
* clocks. Unfortunately many boards don't define a
|
|
* new board Id and simply mangle the
|
|
* CN3010_EVB_HS5
|
|
*/
|
|
if (interface == 0) {
|
|
/*
|
|
* Some boards use a hacked up bootloader that
|
|
* identifies them as CN3010_EVB_HS5
|
|
* evaluation boards. This leads to all kinds
|
|
* of configuration problems. Detect one
|
|
* case, and print warning, while trying to do
|
|
* the right thing.
|
|
*/
|
|
int phy_addr = cvmx_helper_board_get_mii_address(0);
|
|
if (phy_addr != -1) {
|
|
int phy_identifier =
|
|
cvmx_mdio_read(phy_addr >> 8,
|
|
phy_addr & 0xff, 0x2);
|
|
/* Is it a Broadcom PHY? */
|
|
if (phy_identifier == 0x0143) {
|
|
cvmx_dprintf("\n");
|
|
cvmx_dprintf("ERROR:\n");
|
|
cvmx_dprintf
|
|
("ERROR: Board type is CVMX_BOARD_TYPE_CN3010_EVB_HS5, but Broadcom PHY found.\n");
|
|
cvmx_dprintf
|
|
("ERROR: The board type is mis-configured, and software malfunctions are likely.\n");
|
|
cvmx_dprintf
|
|
("ERROR: All boards require a unique board type to identify them.\n");
|
|
cvmx_dprintf("ERROR:\n");
|
|
cvmx_dprintf("\n");
|
|
cvmx_wait(1000000000);
|
|
cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX
|
|
(0, interface), 5);
|
|
cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX
|
|
(0, interface), 5);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return 0;
|
|
}
|