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![Alexander Beregalov](/assets/img/avatar_default.png)
Signed-off-by: Alexander Beregalov <a.beregalov@gmail.com> Cc: Krzysztof Halasa <khc@pm.waw.pl> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
477 lines
13 KiB
C
477 lines
13 KiB
C
/*
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* SBE 2T3E3 synchronous serial card driver for Linux
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*
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* Copyright (C) 2009-2010 Krzysztof Halasa <khc@pm.waw.pl>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License
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* as published by the Free Software Foundation.
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*
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* This code is based on a driver written by SBE Inc.
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*/
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#include <linux/netdevice.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include "2t3e3.h"
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#include "ctrl.h"
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void dc_init(struct channel *sc)
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{
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u32 val;
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dc_stop(sc);
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/*dc_reset(sc);*/ /* do not want to reset here */
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/*
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* BUS_MODE (CSR0)
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*/
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val = SBE_2T3E3_21143_VAL_READ_LINE_ENABLE |
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SBE_2T3E3_21143_VAL_READ_MULTIPLE_ENABLE |
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SBE_2T3E3_21143_VAL_TRANSMIT_AUTOMATIC_POLLING_200us |
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SBE_2T3E3_21143_VAL_BUS_ARBITRATION_RR;
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if (sc->h.command & 16)
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val |= SBE_2T3E3_21143_VAL_WRITE_AND_INVALIDATE_ENABLE;
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switch (sc->h.cache_size) {
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case 32:
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val |= SBE_2T3E3_21143_VAL_CACHE_ALIGNMENT_32;
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break;
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case 16:
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val |= SBE_2T3E3_21143_VAL_CACHE_ALIGNMENT_16;
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break;
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case 8:
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val |= SBE_2T3E3_21143_VAL_CACHE_ALIGNMENT_8;
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break;
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default:
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break;
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}
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dc_write(sc->addr, SBE_2T3E3_21143_REG_BUS_MODE, val);
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/* OPERATION_MODE (CSR6) */
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val = SBE_2T3E3_21143_VAL_RECEIVE_ALL |
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SBE_2T3E3_21143_VAL_MUST_BE_ONE |
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SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS_1 |
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SBE_2T3E3_21143_VAL_LOOPBACK_OFF |
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SBE_2T3E3_21143_VAL_PASS_ALL_MULTICAST |
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SBE_2T3E3_21143_VAL_PROMISCUOUS_MODE |
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SBE_2T3E3_21143_VAL_PASS_BAD_FRAMES;
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dc_write(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE, val);
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if (sc->p.loopback == SBE_2T3E3_LOOPBACK_ETHERNET)
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sc->p.loopback = SBE_2T3E3_LOOPBACK_NONE;
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#if 0 /* No need to clear this register - and it may be in use */
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/*
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* BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT (CSR9)
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*/
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val = 0;
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dc_write(sc->addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT, val);
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#endif
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/*
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* GENERAL_PURPOSE_TIMER_AND_INTERRUPT_MITIGATION_CONTROL (CSR11)
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*/
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val = SBE_2T3E3_21143_VAL_CYCLE_SIZE |
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SBE_2T3E3_21143_VAL_TRANSMIT_TIMER |
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SBE_2T3E3_21143_VAL_NUMBER_OF_TRANSMIT_PACKETS |
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SBE_2T3E3_21143_VAL_RECEIVE_TIMER |
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SBE_2T3E3_21143_VAL_NUMBER_OF_RECEIVE_PACKETS;
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dc_write(sc->addr, SBE_2T3E3_21143_REG_GENERAL_PURPOSE_TIMER_AND_INTERRUPT_MITIGATION_CONTROL, val);
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/* prepare descriptors and data for receive and transmit procecsses */
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if (dc_init_descriptor_list(sc) != 0)
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return;
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/* clear ethernet interrupts status */
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dc_write(sc->addr, SBE_2T3E3_21143_REG_STATUS, 0xFFFFFFFF);
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/* SIA mode registers */
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dc_set_output_port(sc);
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}
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void dc_start(struct channel *sc)
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{
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u32 val;
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if (!(sc->r.flags & SBE_2T3E3_FLAG_NETWORK_UP))
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return;
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dc_init(sc);
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/* get actual LOS and OOF status */
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switch (sc->p.frame_type) {
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case SBE_2T3E3_FRAME_TYPE_E3_G751:
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case SBE_2T3E3_FRAME_TYPE_E3_G832:
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val = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_CONFIGURATION_STATUS_2);
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dev_dbg(&sc->pdev->dev, "Start Framer Rx Status = %02X\n", val);
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sc->s.OOF = val & SBE_2T3E3_FRAMER_VAL_E3_RX_OOF ? 1 : 0;
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break;
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case SBE_2T3E3_FRAME_TYPE_T3_CBIT:
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case SBE_2T3E3_FRAME_TYPE_T3_M13:
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val = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_CONFIGURATION_STATUS);
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dev_dbg(&sc->pdev->dev, "Start Framer Rx Status = %02X\n", val);
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sc->s.OOF = val & SBE_2T3E3_FRAMER_VAL_T3_RX_OOF ? 1 : 0;
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break;
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default:
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break;
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}
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cpld_LOS_update(sc);
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/* start receive and transmit processes */
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dc_transmitter_onoff(sc, SBE_2T3E3_ON);
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dc_receiver_onoff(sc, SBE_2T3E3_ON);
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/* start interrupts */
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dc_start_intr(sc);
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}
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#define MAX_INT_WAIT_CNT 12000
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void dc_stop(struct channel *sc)
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{
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int wcnt;
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/* stop receive and transmit processes */
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dc_receiver_onoff(sc, SBE_2T3E3_OFF);
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dc_transmitter_onoff(sc, SBE_2T3E3_OFF);
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/* turn off ethernet interrupts */
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dc_stop_intr(sc);
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/* wait to ensure the interrupts have been completed */
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for (wcnt = 0; wcnt < MAX_INT_WAIT_CNT; wcnt++) {
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udelay(5);
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if (!sc->interrupt_active)
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break;
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}
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if (wcnt >= MAX_INT_WAIT_CNT)
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dev_warn(&sc->pdev->dev, "SBE 2T3E3: Interrupt active too long\n");
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/* clear all receive/transmit data */
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dc_drop_descriptor_list(sc);
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}
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void dc_start_intr(struct channel *sc)
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{
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if (sc->p.loopback == SBE_2T3E3_LOOPBACK_NONE && sc->s.OOF)
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return;
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if (sc->p.receiver_on || sc->p.transmitter_on) {
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if (!sc->ether.interrupt_enable_mask)
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dc_write(sc->addr, SBE_2T3E3_21143_REG_STATUS, 0xFFFFFFFF);
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sc->ether.interrupt_enable_mask =
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SBE_2T3E3_21143_VAL_NORMAL_INTERRUPT_SUMMARY_ENABLE |
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SBE_2T3E3_21143_VAL_ABNORMAL_INTERRUPT_SUMMARY_ENABLE |
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SBE_2T3E3_21143_VAL_RECEIVE_STOPPED_ENABLE |
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SBE_2T3E3_21143_VAL_RECEIVE_BUFFER_UNAVAILABLE_ENABLE |
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SBE_2T3E3_21143_VAL_RECEIVE_INTERRUPT_ENABLE |
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SBE_2T3E3_21143_VAL_TRANSMIT_UNDERFLOW_INTERRUPT_ENABLE |
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SBE_2T3E3_21143_VAL_TRANSMIT_BUFFER_UNAVAILABLE_ENABLE |
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SBE_2T3E3_21143_VAL_TRANSMIT_STOPPED_ENABLE |
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SBE_2T3E3_21143_VAL_TRANSMIT_INTERRUPT_ENABLE;
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dc_write(sc->addr, SBE_2T3E3_21143_REG_INTERRUPT_ENABLE,
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sc->ether.interrupt_enable_mask);
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}
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}
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void dc_stop_intr(struct channel *sc)
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{
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sc->ether.interrupt_enable_mask = 0;
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dc_write(sc->addr, SBE_2T3E3_21143_REG_INTERRUPT_ENABLE, 0);
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}
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void dc_reset(struct channel *sc)
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{
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/* turn off ethernet interrupts */
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dc_write(sc->addr, SBE_2T3E3_21143_REG_INTERRUPT_ENABLE, 0);
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dc_write(sc->addr, SBE_2T3E3_21143_REG_STATUS, 0xFFFFFFFF);
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/* software reset */
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dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_BUS_MODE,
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SBE_2T3E3_21143_VAL_SOFTWARE_RESET);
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udelay(4); /* 50 PCI cycles < 2us */
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/* clear hardware configuration */
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dc_write(sc->addr, SBE_2T3E3_21143_REG_BUS_MODE, 0);
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/* clear software configuration */
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dc_write(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE, 0);
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/* turn off SIA reset */
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dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_SIA_CONNECTIVITY,
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SBE_2T3E3_21143_VAL_SIA_RESET);
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dc_write(sc->addr, SBE_2T3E3_21143_REG_SIA_TRANSMIT_AND_RECEIVE, 0);
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dc_write(sc->addr, SBE_2T3E3_21143_REG_SIA_AND_GENERAL_PURPOSE_PORT, 0);
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}
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void dc_receiver_onoff(struct channel *sc, u32 mode)
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{
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u32 i, state = 0;
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if (sc->p.receiver_on == mode)
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return;
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switch (mode) {
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case SBE_2T3E3_OFF:
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if (dc_read(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE) &
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SBE_2T3E3_21143_VAL_RECEIVE_START) {
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dc_clear_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
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SBE_2T3E3_21143_VAL_RECEIVE_START);
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for (i = 0; i < 16; i++) {
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state = dc_read(sc->addr, SBE_2T3E3_21143_REG_STATUS) &
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SBE_2T3E3_21143_VAL_RECEIVE_PROCESS_STATE;
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if (state == SBE_2T3E3_21143_VAL_RX_STOPPED)
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break;
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udelay(5);
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}
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if (state != SBE_2T3E3_21143_VAL_RX_STOPPED)
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dev_warn(&sc->pdev->dev, "SBE 2T3E3: Rx failed to stop\n");
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else
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dev_info(&sc->pdev->dev, "SBE 2T3E3: Rx off\n");
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}
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break;
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case SBE_2T3E3_ON:
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dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
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SBE_2T3E3_21143_VAL_RECEIVE_START);
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udelay(100);
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dc_write(sc->addr, SBE_2T3E3_21143_REG_RECEIVE_POLL_DEMAND, 0xFFFFFFFF);
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break;
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default:
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return;
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}
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sc->p.receiver_on = mode;
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}
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void dc_transmitter_onoff(struct channel *sc, u32 mode)
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{
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u32 i, state = 0;
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if (sc->p.transmitter_on == mode)
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return;
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switch (mode) {
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case SBE_2T3E3_OFF:
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if (dc_read(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE) &
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SBE_2T3E3_21143_VAL_TRANSMISSION_START) {
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dc_clear_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
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SBE_2T3E3_21143_VAL_TRANSMISSION_START);
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for (i = 0; i < 16; i++) {
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state = dc_read(sc->addr, SBE_2T3E3_21143_REG_STATUS) &
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SBE_2T3E3_21143_VAL_TRANSMISSION_PROCESS_STATE;
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if (state == SBE_2T3E3_21143_VAL_TX_STOPPED)
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break;
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udelay(5);
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}
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if (state != SBE_2T3E3_21143_VAL_TX_STOPPED)
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dev_warn(&sc->pdev->dev, "SBE 2T3E3: Tx failed to stop\n");
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}
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break;
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case SBE_2T3E3_ON:
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dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
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SBE_2T3E3_21143_VAL_TRANSMISSION_START);
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udelay(100);
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dc_write(sc->addr, SBE_2T3E3_21143_REG_TRANSMIT_POLL_DEMAND, 0xFFFFFFFF);
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break;
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default:
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return;
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}
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sc->p.transmitter_on = mode;
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}
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void dc_set_loopback(struct channel *sc, u32 mode)
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{
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u32 val;
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switch (mode) {
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case SBE_2T3E3_21143_VAL_LOOPBACK_OFF:
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case SBE_2T3E3_21143_VAL_LOOPBACK_INTERNAL:
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break;
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default:
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return;
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}
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#if 0
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/* restart SIA */
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dc_clear_bits(sc->addr, SBE_2T3E3_21143_REG_SIA_CONNECTIVITY,
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SBE_2T3E3_21143_VAL_SIA_RESET);
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udelay(1000);
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dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_SIA_CONNECTIVITY,
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SBE_2T3E3_21143_VAL_SIA_RESET);
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#endif
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/* select loopback mode */
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val = dc_read(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE) &
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~SBE_2T3E3_21143_VAL_OPERATING_MODE;
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val |= mode;
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dc_write(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE, val);
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if (mode == SBE_2T3E3_21143_VAL_LOOPBACK_OFF)
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dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
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SBE_2T3E3_21143_VAL_FULL_DUPLEX_MODE);
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else
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dc_clear_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
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SBE_2T3E3_21143_VAL_FULL_DUPLEX_MODE);
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}
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u32 dc_init_descriptor_list(struct channel *sc)
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{
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u32 i, j;
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struct sk_buff *m;
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if (sc->ether.rx_ring == NULL)
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sc->ether.rx_ring = kzalloc(SBE_2T3E3_RX_DESC_RING_SIZE *
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sizeof(t3e3_rx_desc_t), GFP_KERNEL);
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if (sc->ether.rx_ring == NULL) {
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dev_err(&sc->pdev->dev, "SBE 2T3E3: no buffer space for RX ring\n");
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return ENOMEM;
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}
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if (sc->ether.tx_ring == NULL)
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sc->ether.tx_ring = kzalloc(SBE_2T3E3_TX_DESC_RING_SIZE *
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sizeof(t3e3_tx_desc_t), GFP_KERNEL);
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if (sc->ether.tx_ring == NULL) {
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kfree(sc->ether.rx_ring);
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sc->ether.rx_ring = NULL;
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dev_err(&sc->pdev->dev, "SBE 2T3E3: no buffer space for RX ring\n");
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return ENOMEM;
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}
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/*
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* Receive ring
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*/
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for (i = 0; i < SBE_2T3E3_RX_DESC_RING_SIZE; i++) {
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sc->ether.rx_ring[i].rdes0 = SBE_2T3E3_RX_DESC_21143_OWN;
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sc->ether.rx_ring[i].rdes1 =
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SBE_2T3E3_RX_DESC_SECOND_ADDRESS_CHAINED | SBE_2T3E3_MTU;
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if (sc->ether.rx_data[i] == NULL) {
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if (!(m = dev_alloc_skb(MCLBYTES))) {
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for (j = 0; j < i; j++) {
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dev_kfree_skb_any(sc->ether.rx_data[j]);
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sc->ether.rx_data[j] = NULL;
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}
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kfree(sc->ether.rx_ring);
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sc->ether.rx_ring = NULL;
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kfree(sc->ether.tx_ring);
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sc->ether.tx_ring = NULL;
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dev_err(&sc->pdev->dev, "SBE 2T3E3: token_alloc err:"
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" no buffer space for RX ring\n");
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return ENOBUFS;
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}
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sc->ether.rx_data[i] = m;
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}
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sc->ether.rx_ring[i].rdes2 = virt_to_phys(sc->ether.rx_data[i]->data);
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sc->ether.rx_ring[i].rdes3 = virt_to_phys(
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&sc->ether.rx_ring[(i + 1) % SBE_2T3E3_RX_DESC_RING_SIZE]);
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}
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sc->ether.rx_ring[SBE_2T3E3_RX_DESC_RING_SIZE - 1].rdes1 |=
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SBE_2T3E3_RX_DESC_END_OF_RING;
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sc->ether.rx_ring_current_read = 0;
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dc_write(sc->addr, SBE_2T3E3_21143_REG_RECEIVE_LIST_BASE_ADDRESS,
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virt_to_phys(&sc->ether.rx_ring[0]));
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/*
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* Transmit ring
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*/
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for (i = 0; i < SBE_2T3E3_TX_DESC_RING_SIZE; i++) {
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sc->ether.tx_ring[i].tdes0 = 0;
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sc->ether.tx_ring[i].tdes1 = SBE_2T3E3_TX_DESC_SECOND_ADDRESS_CHAINED |
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SBE_2T3E3_TX_DESC_DISABLE_PADDING;
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sc->ether.tx_ring[i].tdes2 = 0;
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sc->ether.tx_data[i] = NULL;
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sc->ether.tx_ring[i].tdes3 = virt_to_phys(
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&sc->ether.tx_ring[(i + 1) % SBE_2T3E3_TX_DESC_RING_SIZE]);
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}
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sc->ether.tx_ring[SBE_2T3E3_TX_DESC_RING_SIZE - 1].tdes1 |=
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SBE_2T3E3_TX_DESC_END_OF_RING;
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dc_write(sc->addr, SBE_2T3E3_21143_REG_TRANSMIT_LIST_BASE_ADDRESS,
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virt_to_phys(&sc->ether.tx_ring[0]));
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sc->ether.tx_ring_current_read = 0;
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sc->ether.tx_ring_current_write = 0;
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sc->ether.tx_free_cnt = SBE_2T3E3_TX_DESC_RING_SIZE;
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spin_lock_init(&sc->ether.tx_lock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void dc_clear_descriptor_list(struct channel *sc)
|
|
{
|
|
u32 i;
|
|
|
|
/* clear CSR3 and CSR4 */
|
|
dc_write(sc->addr, SBE_2T3E3_21143_REG_RECEIVE_LIST_BASE_ADDRESS, 0);
|
|
dc_write(sc->addr, SBE_2T3E3_21143_REG_TRANSMIT_LIST_BASE_ADDRESS, 0);
|
|
|
|
/* free all data buffers on TX ring */
|
|
for (i = 0; i < SBE_2T3E3_TX_DESC_RING_SIZE; i++) {
|
|
if (sc->ether.tx_data[i] != NULL) {
|
|
dev_kfree_skb_any(sc->ether.tx_data[i]);
|
|
sc->ether.tx_data[i] = NULL;
|
|
}
|
|
}
|
|
}
|
|
|
|
void dc_drop_descriptor_list(struct channel *sc)
|
|
{
|
|
u32 i;
|
|
|
|
dc_clear_descriptor_list(sc);
|
|
|
|
/* free all data buffers on RX ring */
|
|
for (i = 0; i < SBE_2T3E3_RX_DESC_RING_SIZE; i++) {
|
|
if (sc->ether.rx_data[i] != NULL) {
|
|
dev_kfree_skb_any(sc->ether.rx_data[i]);
|
|
sc->ether.rx_data[i] = NULL;
|
|
}
|
|
}
|
|
|
|
kfree(sc->ether.rx_ring);
|
|
sc->ether.rx_ring = NULL;
|
|
kfree(sc->ether.tx_ring);
|
|
sc->ether.tx_ring = NULL;
|
|
}
|
|
|
|
|
|
void dc_set_output_port(struct channel *sc)
|
|
{
|
|
dc_clear_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
|
|
SBE_2T3E3_21143_VAL_PORT_SELECT);
|
|
|
|
dc_write(sc->addr, SBE_2T3E3_21143_REG_SIA_STATUS, 0x00000301);
|
|
dc_write(sc->addr, SBE_2T3E3_21143_REG_SIA_CONNECTIVITY, 0);
|
|
dc_write(sc->addr, SBE_2T3E3_21143_REG_SIA_TRANSMIT_AND_RECEIVE, 0);
|
|
dc_write(sc->addr, SBE_2T3E3_21143_REG_SIA_AND_GENERAL_PURPOSE_PORT, 0x08000011);
|
|
|
|
dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
|
|
SBE_2T3E3_21143_VAL_TRANSMIT_THRESHOLD_MODE_100Mbs |
|
|
SBE_2T3E3_21143_VAL_HEARTBEAT_DISABLE |
|
|
SBE_2T3E3_21143_VAL_PORT_SELECT |
|
|
SBE_2T3E3_21143_VAL_FULL_DUPLEX_MODE);
|
|
}
|
|
|
|
void dc_restart(struct channel *sc)
|
|
{
|
|
dev_warn(&sc->pdev->dev, "SBE 2T3E3: 21143 restart\n");
|
|
|
|
dc_stop(sc);
|
|
dc_reset(sc);
|
|
dc_init(sc); /* stop + reset + init */
|
|
dc_start(sc);
|
|
}
|