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![Krzysztof Halasa](/assets/img/avatar_default.png)
This is a driver for SBE Inc.'s dual port T3/E3 WAN cards. Based on their original GPLed driver. The original driver tarball is now accessible at http://userweb.kernel.org/~chris/SBE_2T3_Linux_2.0c.tgz It needs at least a new generic HDLC setup code (not yet written) before moving to drivers/net/wan. Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
217 lines
7.1 KiB
C
217 lines
7.1 KiB
C
/*
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* SBE 2T3E3 synchronous serial card driver for Linux
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*
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* Copyright (C) 2009-2010 Krzysztof Halasa <khc@pm.waw.pl>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License
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* as published by the Free Software Foundation.
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*
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* This code is based on a driver written by SBE Inc.
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*/
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#include "2t3e3.h"
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#include "ctrl.h"
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void exar7250_init(struct channel *sc)
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{
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exar7250_write(sc, SBE_2T3E3_FRAMER_REG_OPERATING_MODE,
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SBE_2T3E3_FRAMER_VAL_T3_CBIT |
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SBE_2T3E3_FRAMER_VAL_INTERRUPT_ENABLE_RESET |
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SBE_2T3E3_FRAMER_VAL_TIMING_ASYNCH_TXINCLK);
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exar7250_write(sc, SBE_2T3E3_FRAMER_REG_IO_CONTROL,
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SBE_2T3E3_FRAMER_VAL_DISABLE_TX_LOSS_OF_CLOCK |
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SBE_2T3E3_FRAMER_VAL_DISABLE_RX_LOSS_OF_CLOCK |
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SBE_2T3E3_FRAMER_VAL_AMI_LINE_CODE |
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SBE_2T3E3_FRAMER_VAL_RX_LINE_CLOCK_INVERT);
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exar7250_set_frame_type(sc, SBE_2T3E3_FRAME_TYPE_T3_CBIT);
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}
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void exar7250_set_frame_type(struct channel *sc, u32 type)
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{
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u32 val;
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switch (type) {
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case SBE_2T3E3_FRAME_TYPE_E3_G751:
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case SBE_2T3E3_FRAME_TYPE_E3_G832:
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case SBE_2T3E3_FRAME_TYPE_T3_CBIT:
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case SBE_2T3E3_FRAME_TYPE_T3_M13:
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break;
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default:
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return;
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}
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exar7250_stop_intr(sc, type);
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val = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_OPERATING_MODE);
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val &= ~(SBE_2T3E3_FRAMER_VAL_LOCAL_LOOPBACK_MODE |
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SBE_2T3E3_FRAMER_VAL_T3_E3_SELECT |
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SBE_2T3E3_FRAMER_VAL_FRAME_FORMAT_SELECT);
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switch (type) {
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case SBE_2T3E3_FRAME_TYPE_E3_G751:
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val |= SBE_2T3E3_FRAMER_VAL_E3_G751;
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break;
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case SBE_2T3E3_FRAME_TYPE_E3_G832:
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val |= SBE_2T3E3_FRAMER_VAL_E3_G832;
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break;
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case SBE_2T3E3_FRAME_TYPE_T3_CBIT:
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val |= SBE_2T3E3_FRAMER_VAL_T3_CBIT;
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break;
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case SBE_2T3E3_FRAME_TYPE_T3_M13:
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val |= SBE_2T3E3_FRAMER_VAL_T3_M13;
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break;
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default:
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return;
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}
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exar7250_write(sc, SBE_2T3E3_FRAMER_REG_OPERATING_MODE, val);
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exar7250_start_intr(sc, type);
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}
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void exar7250_start_intr(struct channel *sc, u32 type)
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{
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u32 val;
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switch (type) {
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case SBE_2T3E3_FRAME_TYPE_E3_G751:
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case SBE_2T3E3_FRAME_TYPE_E3_G832:
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val = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_CONFIGURATION_STATUS_2);
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#if 0
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sc->s.LOS = val & SBE_2T3E3_FRAMER_VAL_E3_RX_LOS ? 1 : 0;
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#else
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cpld_LOS_update(sc);
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#endif
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sc->s.OOF = val & SBE_2T3E3_FRAMER_VAL_E3_RX_OOF ? 1 : 0;
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exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_STATUS_1);
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exar7250_write(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_ENABLE_1,
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SBE_2T3E3_FRAMER_VAL_E3_RX_OOF_INTERRUPT_ENABLE |
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SBE_2T3E3_FRAMER_VAL_E3_RX_LOS_INTERRUPT_ENABLE);
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#if 0
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/*SBE_2T3E3_FRAMER_VAL_E3_RX_COFA_INTERRUPT_ENABLE |
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SBE_2T3E3_FRAMER_VAL_E3_RX_OOF_INTERRUPT_ENABLE |
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SBE_2T3E3_FRAMER_VAL_E3_RX_LOF_INTERRUPT_ENABLE |
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SBE_2T3E3_FRAMER_VAL_E3_RX_LOS_INTERRUPT_ENABLE |
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SBE_2T3E3_FRAMER_VAL_E3_RX_AIS_INTERRUPT_ENABLE);*/
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#endif
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exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_STATUS_2);
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#if 0
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exar7250_write(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_ENABLE_2,
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SBE_2T3E3_FRAMER_VAL_E3_RX_FEBE_INTERRUPT_ENABLE |
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SBE_2T3E3_FRAMER_VAL_E3_RX_FERF_INTERRUPT_ENABLE |
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SBE_2T3E3_FRAMER_VAL_E3_RX_FRAMING_BYTE_ERROR_INTERRUPT_ENABLE);
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#endif
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break;
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case SBE_2T3E3_FRAME_TYPE_T3_CBIT:
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case SBE_2T3E3_FRAME_TYPE_T3_M13:
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val = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_CONFIGURATION_STATUS);
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#if 0
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sc->s.LOS = val & SBE_2T3E3_FRAMER_VAL_T3_RX_LOS ? 1 : 0;
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#else
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cpld_LOS_update(sc);
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#endif
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sc->s.OOF = val & SBE_2T3E3_FRAMER_VAL_T3_RX_OOF ? 1 : 0;
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exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_INTERRUPT_STATUS);
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exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_RX_INTERRUPT_ENABLE,
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SBE_2T3E3_FRAMER_VAL_T3_RX_LOS_INTERRUPT_ENABLE |
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SBE_2T3E3_FRAMER_VAL_T3_RX_OOF_INTERRUPT_ENABLE);
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#if 0
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/* SBE_2T3E3_FRAMER_VAL_T3_RX_CP_BIT_ERROR_INTERRUPT_ENABLE |
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SBE_2T3E3_FRAMER_VAL_T3_RX_LOS_INTERRUPT_ENABLE |
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SBE_2T3E3_FRAMER_VAL_T3_RX_AIS_INTERRUPT_ENABLE |
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SBE_2T3E3_FRAMER_VAL_T3_RX_IDLE_INTERRUPT_ENABLE |
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SBE_2T3E3_FRAMER_VAL_T3_RX_FERF_INTERRUPT_ENABLE |
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SBE_2T3E3_FRAMER_VAL_T3_RX_AIC_INTERRUPT_ENABLE |
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SBE_2T3E3_FRAMER_VAL_T3_RX_OOF_INTERRUPT_ENABLE |
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SBE_2T3E3_FRAMER_VAL_T3_RX_P_BIT_INTERRUPT_ENABLE);*/
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#endif
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exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_FEAC_INTERRUPT_ENABLE_STATUS);
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#if 0
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exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_RX_FEAC_INTERRUPT_ENABLE_STATUS,
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SBE_2T3E3_FRAMER_VAL_T3_RX_FEAC_REMOVE_INTERRUPT_ENABLE |
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SBE_2T3E3_FRAMER_VAL_T3_RX_FEAC_VALID_INTERRUPT_ENABLE);
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#endif
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exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_RX_LAPD_CONTROL, 0);
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break;
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default:
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return;
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}
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exar7250_read(sc, SBE_2T3E3_FRAMER_REG_BLOCK_INTERRUPT_STATUS);
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exar7250_write(sc, SBE_2T3E3_FRAMER_REG_BLOCK_INTERRUPT_ENABLE,
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SBE_2T3E3_FRAMER_VAL_RX_INTERRUPT_ENABLE |
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SBE_2T3E3_FRAMER_VAL_TX_INTERRUPT_ENABLE);
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}
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void exar7250_stop_intr(struct channel *sc, u32 type)
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{
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exar7250_write(sc, SBE_2T3E3_FRAMER_REG_BLOCK_INTERRUPT_ENABLE, 0);
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exar7250_read(sc, SBE_2T3E3_FRAMER_REG_BLOCK_INTERRUPT_STATUS);
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switch (type) {
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case SBE_2T3E3_FRAME_TYPE_E3_G751:
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case SBE_2T3E3_FRAME_TYPE_E3_G832:
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exar7250_write(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_ENABLE_1, 0);
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exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_STATUS_1);
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exar7250_write(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_ENABLE_2, 0);
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exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_STATUS_2);
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exar7250_write(sc, SBE_2T3E3_FRAMER_REG_E3_RX_LAPD_CONTROL, 0);
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exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_LAPD_CONTROL);
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exar7250_write(sc, SBE_2T3E3_FRAMER_REG_E3_TX_LAPD_STATUS, 0);
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exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_TX_LAPD_STATUS);
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break;
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case SBE_2T3E3_FRAME_TYPE_T3_CBIT:
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case SBE_2T3E3_FRAME_TYPE_T3_M13:
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exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_RX_INTERRUPT_ENABLE, 0);
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exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_INTERRUPT_STATUS);
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exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_RX_FEAC_INTERRUPT_ENABLE_STATUS, 0);
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exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_FEAC_INTERRUPT_ENABLE_STATUS);
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exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_RX_LAPD_CONTROL, 0);
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exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_LAPD_CONTROL);
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exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_TX_FEAC_CONFIGURATION_STATUS, 0);
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exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_TX_FEAC_CONFIGURATION_STATUS);
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exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_TX_LAPD_STATUS, 0);
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exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_TX_LAPD_STATUS);
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break;
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}
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}
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void exar7250_unipolar_onoff(struct channel *sc, u32 mode)
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{
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switch (mode) {
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case SBE_2T3E3_OFF:
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exar7300_clear_bit(sc, SBE_2T3E3_FRAMER_REG_IO_CONTROL,
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SBE_2T3E3_FRAMER_VAL_UNIPOLAR);
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break;
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case SBE_2T3E3_ON:
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exar7300_set_bit(sc, SBE_2T3E3_FRAMER_REG_IO_CONTROL,
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SBE_2T3E3_FRAMER_VAL_UNIPOLAR);
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break;
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}
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}
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void exar7250_set_loopback(struct channel *sc, u32 mode)
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{
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switch (mode) {
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case SBE_2T3E3_FRAMER_VAL_LOOPBACK_OFF:
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exar7300_clear_bit(sc, SBE_2T3E3_FRAMER_REG_OPERATING_MODE,
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SBE_2T3E3_FRAMER_VAL_LOCAL_LOOPBACK_MODE);
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break;
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case SBE_2T3E3_FRAMER_VAL_LOOPBACK_ON:
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exar7300_set_bit(sc, SBE_2T3E3_FRAMER_REG_OPERATING_MODE,
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SBE_2T3E3_FRAMER_VAL_LOCAL_LOOPBACK_MODE);
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break;
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}
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}
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