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![David Woodhouse](/assets/img/avatar_default.png)
It'll take some work before this is really shippable. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
131 lines
4.3 KiB
C
131 lines
4.3 KiB
C
/*
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* NAND Flash Controller Device Driver
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* Copyright (c) 2009, Intel Corporation and its suppliers.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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*/
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#ifndef _LLD_NAND_
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#define _LLD_NAND_
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#ifdef ELDORA
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#include "defs.h"
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#else
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#include "flash.h"
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#include "ffsport.h"
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#endif
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#define MODE_00 0x00000000
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#define MODE_01 0x04000000
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#define MODE_10 0x08000000
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#define MODE_11 0x0C000000
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#define DATA_TRANSFER_MODE 0
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#define PROTECTION_PER_BLOCK 1
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#define LOAD_WAIT_COUNT 2
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#define PROGRAM_WAIT_COUNT 3
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#define ERASE_WAIT_COUNT 4
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#define INT_MONITOR_CYCLE_COUNT 5
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#define READ_BUSY_PIN_ENABLED 6
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#define MULTIPLANE_OPERATION_SUPPORT 7
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#define PRE_FETCH_MODE 8
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#define CE_DONT_CARE_SUPPORT 9
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#define COPYBACK_SUPPORT 10
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#define CACHE_WRITE_SUPPORT 11
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#define CACHE_READ_SUPPORT 12
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#define NUM_PAGES_IN_BLOCK 13
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#define ECC_ENABLE_SELECT 14
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#define WRITE_ENABLE_2_READ_ENABLE 15
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#define ADDRESS_2_DATA 16
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#define READ_ENABLE_2_WRITE_ENABLE 17
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#define TWO_ROW_ADDRESS_CYCLES 18
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#define MULTIPLANE_ADDRESS_RESTRICT 19
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#define ACC_CLOCKS 20
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#define READ_WRITE_ENABLE_LOW_COUNT 21
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#define READ_WRITE_ENABLE_HIGH_COUNT 22
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#define ECC_SECTOR_SIZE 512
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#define LLD_MAX_FLASH_BANKS 4
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struct mrst_nand_info {
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struct pci_dev *dev;
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u32 state;
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u32 flash_bank;
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u8 *read_data;
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u8 *write_data;
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u32 block;
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u16 page;
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u32 use_dma;
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void __iomem *ioaddr; /* Mapped io reg base address */
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int ret;
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u32 pcmds_num;
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struct pending_cmd *pcmds;
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int cdma_num; /* CDMA descriptor number in this chan */
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u8 *cdma_desc_buf; /* CDMA descriptor table */
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u8 *memcp_desc_buf; /* Memory copy descriptor table */
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dma_addr_t cdma_desc; /* Mapped CDMA descriptor table */
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dma_addr_t memcp_desc; /* Mapped memory copy descriptor table */
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struct completion complete;
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};
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int NAND_Flash_Init(void);
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int nand_release_spectra(void);
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u16 NAND_Flash_Reset(void);
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u16 NAND_Read_Device_ID(void);
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u16 NAND_Erase_Block(u32 flash_add);
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u16 NAND_Write_Page_Main(u8 *write_data, u32 block, u16 page,
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u16 page_count);
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u16 NAND_Read_Page_Main(u8 *read_data, u32 block, u16 page,
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u16 page_count);
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u16 NAND_UnlockArrayAll(void);
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u16 NAND_Write_Page_Main_Spare(u8 *write_data, u32 block,
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u16 page, u16 page_count);
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u16 NAND_Write_Page_Spare(u8 *read_data, u32 block, u16 page,
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u16 page_count);
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u16 NAND_Read_Page_Main_Spare(u8 *read_data, u32 block, u16 page,
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u16 page_count);
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u16 NAND_Read_Page_Spare(u8 *read_data, u32 block, u16 page,
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u16 page_count);
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void NAND_LLD_Enable_Disable_Interrupts(u16 INT_ENABLE);
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u16 NAND_Get_Bad_Block(u32 block);
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u16 NAND_Pipeline_Read_Ahead(u8 *read_data, u32 block, u16 page,
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u16 page_count);
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u16 NAND_Pipeline_Write_Ahead(u8 *write_data, u32 block,
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u16 page, u16 page_count);
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u16 NAND_Multiplane_Read(u8 *read_data, u32 block, u16 page,
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u16 page_count);
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u16 NAND_Multiplane_Write(u8 *write_data, u32 block, u16 page,
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u16 page_count);
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void NAND_ECC_Ctrl(int enable);
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u16 NAND_Read_Page_Main_Polling(u8 *read_data,
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u32 block, u16 page, u16 page_count);
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u16 NAND_Pipeline_Read_Ahead_Polling(u8 *read_data,
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u32 block, u16 page, u16 page_count);
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void Conv_Spare_Data_Log2Phy_Format(u8 *data);
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void Conv_Spare_Data_Phy2Log_Format(u8 *data);
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void Conv_Main_Spare_Data_Log2Phy_Format(u8 *data, u16 page_count);
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void Conv_Main_Spare_Data_Phy2Log_Format(u8 *data, u16 page_count);
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extern void __iomem *FlashReg;
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extern void __iomem *FlashMem;
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extern int totalUsedBanks;
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extern u32 GLOB_valid_banks[LLD_MAX_FLASH_BANKS];
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#endif /*_LLD_NAND_*/
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