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4539c24fe4
Tegra's UART is currently auto-detected as PORT_XSCALE due to register bit UART_IER.UUE being writable. However, the Tegra documentation states that this register bit is reserved. Hence, we should not program it. Instead, the documentation specifies that the UART is 16550 compatible. However, Tegra does need register bit UART_IER.RTOIE set, which is not enabled by any 16550 port type. This was not noticed before, since PORT_XSCALE enables CAP_UUE, which conflates both UUE and RTOIE bit programming. This change defines PORT_TEGRA that doesn't set UART_CAP_UUE, but does set UART_CAP_RTOIE, which is a new capability indicating that the RTOIE bit needs to be enabled. Based-on-code-by: Laxman Dewangan <ldewangan@nvidia.com> Cc: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
79 lines
2.4 KiB
C
79 lines
2.4 KiB
C
/*
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* Driver for 8250/16550-type serial ports
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*
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* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
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*
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* Copyright (C) 2001 Russell King.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/serial_8250.h>
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struct old_serial_port {
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unsigned int uart;
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unsigned int baud_base;
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unsigned int port;
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unsigned int irq;
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unsigned int flags;
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unsigned char hub6;
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unsigned char io_type;
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unsigned char *iomem_base;
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unsigned short iomem_reg_shift;
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unsigned long irqflags;
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};
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/*
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* This replaces serial_uart_config in include/linux/serial.h
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*/
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struct serial8250_config {
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const char *name;
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unsigned short fifo_size;
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unsigned short tx_loadsz;
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unsigned char fcr;
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unsigned int flags;
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};
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#define UART_CAP_FIFO (1 << 8) /* UART has FIFO */
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#define UART_CAP_EFR (1 << 9) /* UART has EFR */
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#define UART_CAP_SLEEP (1 << 10) /* UART has IER sleep */
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#define UART_CAP_AFE (1 << 11) /* MCR-based hw flow control */
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#define UART_CAP_UUE (1 << 12) /* UART needs IER bit 6 set (Xscale) */
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#define UART_CAP_RTOIE (1 << 13) /* UART needs IER bit 4 set (Xscale, Tegra) */
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#define UART_BUG_QUOT (1 << 0) /* UART has buggy quot LSB */
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#define UART_BUG_TXEN (1 << 1) /* UART has buggy TX IIR status */
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#define UART_BUG_NOMSR (1 << 2) /* UART has buggy MSR status bits (Au1x00) */
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#define UART_BUG_THRE (1 << 3) /* UART has buggy THRE reassertion */
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#define PROBE_RSA (1 << 0)
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#define PROBE_ANY (~0)
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#define HIGH_BITS_OFFSET ((sizeof(long)-sizeof(int))*8)
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#ifdef CONFIG_SERIAL_8250_SHARE_IRQ
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#define SERIAL8250_SHARE_IRQS 1
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#else
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#define SERIAL8250_SHARE_IRQS 0
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#endif
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#if defined(__alpha__) && !defined(CONFIG_PCI)
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/*
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* Digital did something really horribly wrong with the OUT1 and OUT2
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* lines on at least some ALPHA's. The failure mode is that if either
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* is cleared, the machine locks up with endless interrupts.
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*/
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#define ALPHA_KLUDGE_MCR (UART_MCR_OUT2 | UART_MCR_OUT1)
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#elif defined(CONFIG_SBC8560)
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/*
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* WindRiver did something similarly broken on their SBC8560 board. The
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* UART tristates its IRQ output while OUT2 is clear, but they pulled
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* the interrupt line _up_ instead of down, so if we register the IRQ
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* while the UART is in that state, we die in an IRQ storm. */
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#define ALPHA_KLUDGE_MCR (UART_MCR_OUT2)
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#else
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#define ALPHA_KLUDGE_MCR 0
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#endif
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