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0fdebc5ec2
Based on the normalized pattern:
this file is licensed under the terms of the gnu general public
license version 2 this program is licensed as is without any warranty
of any kind whether express or implied
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference.
Reviewed-by: Allison Randal <allison@lohutok.net>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
65 lines
2.1 KiB
C
65 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* AM43x PRCM defines
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H
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#define __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H
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#define AM43XX_PRM_PARTITION 1
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#define AM43XX_CM_PARTITION 1
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/* PRM instances */
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#define AM43XX_PRM_OCP_SOCKET_INST 0x0000
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#define AM43XX_PRM_MPU_INST 0x0300
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#define AM43XX_PRM_GFX_INST 0x0400
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#define AM43XX_PRM_RTC_INST 0x0500
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#define AM43XX_PRM_TAMPER_INST 0x0600
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#define AM43XX_PRM_CEFUSE_INST 0x0700
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#define AM43XX_PRM_PER_INST 0x0800
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#define AM43XX_PRM_WKUP_INST 0x2000
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#define AM43XX_PRM_DEVICE_INST 0x4000
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/* PRM_IRQ offsets */
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#define AM43XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004
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#define AM43XX_PRM_IRQENABLE_MPU_OFFSET 0x0008
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/* Other PRM offsets */
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#define AM43XX_PRM_IO_PMCTRL_OFFSET 0x0024
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/* CM instances */
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#define AM43XX_CM_WKUP_INST 0x2800
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#define AM43XX_CM_MPU_INST 0x8300
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#define AM43XX_CM_GFX_INST 0x8400
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#define AM43XX_CM_RTC_INST 0x8500
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#define AM43XX_CM_TAMPER_INST 0x8600
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#define AM43XX_CM_CEFUSE_INST 0x8700
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#define AM43XX_CM_PER_INST 0x8800
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/* CD offsets */
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#define AM43XX_CM_WKUP_L3_AON_CDOFFS 0x0000
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#define AM43XX_CM_WKUP_L3S_TSC_CDOFFS 0x0100
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#define AM43XX_CM_WKUP_L4_WKUP_AON_CDOFFS 0x0200
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#define AM43XX_CM_WKUP_WKUP_CDOFFS 0x0300
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#define AM43XX_CM_MPU_MPU_CDOFFS 0x0000
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#define AM43XX_CM_GFX_GFX_L3_CDOFFS 0x0000
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#define AM43XX_CM_RTC_RTC_CDOFFS 0x0000
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#define AM43XX_CM_TAMPER_TAMPER_CDOFFS 0x0000
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#define AM43XX_CM_CEFUSE_CEFUSE_CDOFFS 0x0000
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#define AM43XX_CM_PER_L3_CDOFFS 0x0000
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#define AM43XX_CM_PER_L3S_CDOFFS 0x0200
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#define AM43XX_CM_PER_ICSS_CDOFFS 0x0300
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#define AM43XX_CM_PER_L4LS_CDOFFS 0x0400
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#define AM43XX_CM_PER_EMIF_CDOFFS 0x0700
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#define AM43XX_CM_PER_LCDC_CDOFFS 0x0800
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#define AM43XX_CM_PER_DSS_CDOFFS 0x0a00
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#define AM43XX_CM_PER_CPSW_CDOFFS 0x0b00
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#define AM43XX_CM_PER_OCPWP_L3_CDOFFS 0x0c00
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/* CLK CTRL offsets */
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#define AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020
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#define AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET 0x0720
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#endif
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