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![Alison Schofield](/assets/img/avatar_default.png)
During NUMA init, CXL memory defined in the SRAT Memory Affinity subtable may be assigned to a NUMA node. Since there is no requirement that the SRAT be comprehensive for CXL memory another mechanism is needed to assign NUMA nodes to CXL memory not identified in the SRAT. Use the CXL Fixed Memory Window Structure (CFMWS) of the ACPI CXL Early Discovery Table (CEDT) to find all CXL memory ranges. Create a NUMA node for each CFMWS that is not already assigned to a NUMA node. Add a memblk attaching its host physical address range to the node. Note that these ranges may not actually map any memory at boot time. They may describe persistent capacity or may be present to enable hot-plug. Consumers can use phys_to_target_node() to discover the NUMA node. Signed-off-by: Alison Schofield <alison.schofield@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://lore.kernel.org/r/163553711933.2509508.2203471175679990.stgit@dwillia2-desk3.amr.corp.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
436 lines
11 KiB
C
436 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright(c) 2021 Intel Corporation. All rights reserved. */
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/acpi.h>
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#include <linux/pci.h>
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#include "cxl.h"
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/* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */
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#define CFMWS_INTERLEAVE_WAYS(x) (1 << (x)->interleave_ways)
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#define CFMWS_INTERLEAVE_GRANULARITY(x) ((x)->granularity + 8)
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static unsigned long cfmws_to_decoder_flags(int restrictions)
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{
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unsigned long flags = 0;
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if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE2)
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flags |= CXL_DECODER_F_TYPE2;
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if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE3)
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flags |= CXL_DECODER_F_TYPE3;
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if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_VOLATILE)
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flags |= CXL_DECODER_F_RAM;
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if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_PMEM)
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flags |= CXL_DECODER_F_PMEM;
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if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_FIXED)
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flags |= CXL_DECODER_F_LOCK;
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return flags;
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}
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static int cxl_acpi_cfmws_verify(struct device *dev,
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struct acpi_cedt_cfmws *cfmws)
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{
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int expected_len;
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if (cfmws->interleave_arithmetic != ACPI_CEDT_CFMWS_ARITHMETIC_MODULO) {
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dev_err(dev, "CFMWS Unsupported Interleave Arithmetic\n");
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return -EINVAL;
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}
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if (!IS_ALIGNED(cfmws->base_hpa, SZ_256M)) {
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dev_err(dev, "CFMWS Base HPA not 256MB aligned\n");
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return -EINVAL;
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}
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if (!IS_ALIGNED(cfmws->window_size, SZ_256M)) {
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dev_err(dev, "CFMWS Window Size not 256MB aligned\n");
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return -EINVAL;
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}
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if (CFMWS_INTERLEAVE_WAYS(cfmws) > CXL_DECODER_MAX_INTERLEAVE) {
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dev_err(dev, "CFMWS Interleave Ways (%d) too large\n",
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CFMWS_INTERLEAVE_WAYS(cfmws));
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return -EINVAL;
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}
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expected_len = struct_size((cfmws), interleave_targets,
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CFMWS_INTERLEAVE_WAYS(cfmws));
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if (cfmws->header.length < expected_len) {
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dev_err(dev, "CFMWS length %d less than expected %d\n",
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cfmws->header.length, expected_len);
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return -EINVAL;
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}
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if (cfmws->header.length > expected_len)
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dev_dbg(dev, "CFMWS length %d greater than expected %d\n",
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cfmws->header.length, expected_len);
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return 0;
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}
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struct cxl_cfmws_context {
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struct device *dev;
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struct cxl_port *root_port;
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};
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static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg,
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const unsigned long end)
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{
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int target_map[CXL_DECODER_MAX_INTERLEAVE];
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struct cxl_cfmws_context *ctx = arg;
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struct cxl_port *root_port = ctx->root_port;
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struct device *dev = ctx->dev;
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struct acpi_cedt_cfmws *cfmws;
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struct cxl_decoder *cxld;
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int rc, i;
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cfmws = (struct acpi_cedt_cfmws *) header;
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rc = cxl_acpi_cfmws_verify(dev, cfmws);
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if (rc) {
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dev_err(dev, "CFMWS range %#llx-%#llx not registered\n",
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cfmws->base_hpa,
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cfmws->base_hpa + cfmws->window_size - 1);
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return 0;
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}
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for (i = 0; i < CFMWS_INTERLEAVE_WAYS(cfmws); i++)
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target_map[i] = cfmws->interleave_targets[i];
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cxld = cxl_decoder_alloc(root_port, CFMWS_INTERLEAVE_WAYS(cfmws));
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if (IS_ERR(cxld))
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return 0;
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cxld->flags = cfmws_to_decoder_flags(cfmws->restrictions);
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cxld->target_type = CXL_DECODER_EXPANDER;
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cxld->range = (struct range){
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.start = cfmws->base_hpa,
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.end = cfmws->base_hpa + cfmws->window_size - 1,
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};
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cxld->interleave_ways = CFMWS_INTERLEAVE_WAYS(cfmws);
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cxld->interleave_granularity = CFMWS_INTERLEAVE_GRANULARITY(cfmws);
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rc = cxl_decoder_add(cxld, target_map);
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if (rc)
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put_device(&cxld->dev);
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else
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rc = cxl_decoder_autoremove(dev, cxld);
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if (rc) {
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dev_err(dev, "Failed to add decoder for %#llx-%#llx\n",
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cfmws->base_hpa,
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cfmws->base_hpa + cfmws->window_size - 1);
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return 0;
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}
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dev_dbg(dev, "add: %s node: %d range %#llx-%#llx\n",
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dev_name(&cxld->dev), phys_to_target_node(cxld->range.start),
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cfmws->base_hpa, cfmws->base_hpa + cfmws->window_size - 1);
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return 0;
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}
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__mock int match_add_root_ports(struct pci_dev *pdev, void *data)
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{
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struct cxl_walk_context *ctx = data;
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struct pci_bus *root_bus = ctx->root;
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struct cxl_port *port = ctx->port;
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int type = pci_pcie_type(pdev);
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struct device *dev = ctx->dev;
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u32 lnkcap, port_num;
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int rc;
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if (pdev->bus != root_bus)
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return 0;
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if (!pci_is_pcie(pdev))
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return 0;
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if (type != PCI_EXP_TYPE_ROOT_PORT)
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return 0;
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if (pci_read_config_dword(pdev, pci_pcie_cap(pdev) + PCI_EXP_LNKCAP,
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&lnkcap) != PCIBIOS_SUCCESSFUL)
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return 0;
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/* TODO walk DVSEC to find component register base */
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port_num = FIELD_GET(PCI_EXP_LNKCAP_PN, lnkcap);
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rc = cxl_add_dport(port, &pdev->dev, port_num, CXL_RESOURCE_NONE);
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if (rc) {
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ctx->error = rc;
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return rc;
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}
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ctx->count++;
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dev_dbg(dev, "add dport%d: %s\n", port_num, dev_name(&pdev->dev));
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return 0;
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}
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static struct cxl_dport *find_dport_by_dev(struct cxl_port *port, struct device *dev)
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{
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struct cxl_dport *dport;
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device_lock(&port->dev);
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list_for_each_entry(dport, &port->dports, list)
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if (dport->dport == dev) {
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device_unlock(&port->dev);
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return dport;
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}
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device_unlock(&port->dev);
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return NULL;
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}
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__mock struct acpi_device *to_cxl_host_bridge(struct device *host,
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struct device *dev)
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{
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struct acpi_device *adev = to_acpi_device(dev);
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if (!acpi_pci_find_root(adev->handle))
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return NULL;
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if (strcmp(acpi_device_hid(adev), "ACPI0016") == 0)
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return adev;
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return NULL;
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}
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/*
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* A host bridge is a dport to a CFMWS decode and it is a uport to the
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* dport (PCIe Root Ports) in the host bridge.
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*/
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static int add_host_bridge_uport(struct device *match, void *arg)
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{
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struct cxl_port *root_port = arg;
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struct device *host = root_port->dev.parent;
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struct acpi_device *bridge = to_cxl_host_bridge(host, match);
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struct acpi_pci_root *pci_root;
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struct cxl_walk_context ctx;
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int single_port_map[1], rc;
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struct cxl_decoder *cxld;
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struct cxl_dport *dport;
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struct cxl_port *port;
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if (!bridge)
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return 0;
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dport = find_dport_by_dev(root_port, match);
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if (!dport) {
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dev_dbg(host, "host bridge expected and not found\n");
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return 0;
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}
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port = devm_cxl_add_port(host, match, dport->component_reg_phys,
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root_port);
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if (IS_ERR(port))
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return PTR_ERR(port);
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dev_dbg(host, "%s: add: %s\n", dev_name(match), dev_name(&port->dev));
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/*
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* Note that this lookup already succeeded in
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* to_cxl_host_bridge(), so no need to check for failure here
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*/
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pci_root = acpi_pci_find_root(bridge->handle);
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ctx = (struct cxl_walk_context){
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.dev = host,
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.root = pci_root->bus,
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.port = port,
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};
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pci_walk_bus(pci_root->bus, match_add_root_ports, &ctx);
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if (ctx.count == 0)
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return -ENODEV;
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if (ctx.error)
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return ctx.error;
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if (ctx.count > 1)
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return 0;
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/* TODO: Scan CHBCR for HDM Decoder resources */
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/*
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* Per the CXL specification (8.2.5.12 CXL HDM Decoder Capability
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* Structure) single ported host-bridges need not publish a decoder
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* capability when a passthrough decode can be assumed, i.e. all
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* transactions that the uport sees are claimed and passed to the single
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* dport. Disable the range until the first CXL region is enumerated /
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* activated.
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*/
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cxld = cxl_decoder_alloc(port, 1);
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if (IS_ERR(cxld))
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return PTR_ERR(cxld);
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cxld->interleave_ways = 1;
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cxld->interleave_granularity = PAGE_SIZE;
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cxld->target_type = CXL_DECODER_EXPANDER;
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cxld->range = (struct range) {
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.start = 0,
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.end = -1,
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};
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device_lock(&port->dev);
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dport = list_first_entry(&port->dports, typeof(*dport), list);
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device_unlock(&port->dev);
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single_port_map[0] = dport->port_id;
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rc = cxl_decoder_add(cxld, single_port_map);
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if (rc)
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put_device(&cxld->dev);
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else
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rc = cxl_decoder_autoremove(host, cxld);
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if (rc == 0)
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dev_dbg(host, "add: %s\n", dev_name(&cxld->dev));
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return rc;
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}
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struct cxl_chbs_context {
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struct device *dev;
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unsigned long long uid;
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resource_size_t chbcr;
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};
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static int cxl_get_chbcr(union acpi_subtable_headers *header, void *arg,
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const unsigned long end)
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{
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struct cxl_chbs_context *ctx = arg;
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struct acpi_cedt_chbs *chbs;
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if (ctx->chbcr)
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return 0;
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chbs = (struct acpi_cedt_chbs *) header;
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if (ctx->uid != chbs->uid)
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return 0;
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ctx->chbcr = chbs->base;
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return 0;
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}
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static int add_host_bridge_dport(struct device *match, void *arg)
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{
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int rc;
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acpi_status status;
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unsigned long long uid;
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struct cxl_chbs_context ctx;
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struct cxl_port *root_port = arg;
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struct device *host = root_port->dev.parent;
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struct acpi_device *bridge = to_cxl_host_bridge(host, match);
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if (!bridge)
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return 0;
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status = acpi_evaluate_integer(bridge->handle, METHOD_NAME__UID, NULL,
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&uid);
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if (status != AE_OK) {
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dev_err(host, "unable to retrieve _UID of %s\n",
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dev_name(match));
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return -ENODEV;
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}
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ctx = (struct cxl_chbs_context) {
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.dev = host,
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.uid = uid,
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};
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acpi_table_parse_cedt(ACPI_CEDT_TYPE_CHBS, cxl_get_chbcr, &ctx);
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if (ctx.chbcr == 0) {
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dev_warn(host, "No CHBS found for Host Bridge: %s\n",
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dev_name(match));
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return 0;
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}
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rc = cxl_add_dport(root_port, match, uid, ctx.chbcr);
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if (rc) {
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dev_err(host, "failed to add downstream port: %s\n",
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dev_name(match));
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return rc;
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}
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dev_dbg(host, "add dport%llu: %s\n", uid, dev_name(match));
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return 0;
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}
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static int add_root_nvdimm_bridge(struct device *match, void *data)
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{
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struct cxl_decoder *cxld;
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struct cxl_port *root_port = data;
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struct cxl_nvdimm_bridge *cxl_nvb;
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struct device *host = root_port->dev.parent;
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if (!is_root_decoder(match))
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return 0;
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cxld = to_cxl_decoder(match);
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if (!(cxld->flags & CXL_DECODER_F_PMEM))
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return 0;
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cxl_nvb = devm_cxl_add_nvdimm_bridge(host, root_port);
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if (IS_ERR(cxl_nvb)) {
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dev_dbg(host, "failed to register pmem\n");
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return PTR_ERR(cxl_nvb);
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}
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dev_dbg(host, "%s: add: %s\n", dev_name(&root_port->dev),
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dev_name(&cxl_nvb->dev));
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return 1;
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}
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static int cxl_acpi_probe(struct platform_device *pdev)
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{
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int rc;
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struct cxl_port *root_port;
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struct device *host = &pdev->dev;
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struct acpi_device *adev = ACPI_COMPANION(host);
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struct cxl_cfmws_context ctx;
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root_port = devm_cxl_add_port(host, host, CXL_RESOURCE_NONE, NULL);
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if (IS_ERR(root_port))
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return PTR_ERR(root_port);
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dev_dbg(host, "add: %s\n", dev_name(&root_port->dev));
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rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
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add_host_bridge_dport);
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if (rc < 0)
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return rc;
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ctx = (struct cxl_cfmws_context) {
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.dev = host,
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.root_port = root_port,
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};
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acpi_table_parse_cedt(ACPI_CEDT_TYPE_CFMWS, cxl_parse_cfmws, &ctx);
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/*
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* Root level scanned with host-bridge as dports, now scan host-bridges
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* for their role as CXL uports to their CXL-capable PCIe Root Ports.
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*/
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rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
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add_host_bridge_uport);
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if (rc < 0)
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return rc;
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if (IS_ENABLED(CONFIG_CXL_PMEM))
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rc = device_for_each_child(&root_port->dev, root_port,
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add_root_nvdimm_bridge);
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if (rc < 0)
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return rc;
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return 0;
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}
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static const struct acpi_device_id cxl_acpi_ids[] = {
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{ "ACPI0017" },
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{ },
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};
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MODULE_DEVICE_TABLE(acpi, cxl_acpi_ids);
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static struct platform_driver cxl_acpi_driver = {
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.probe = cxl_acpi_probe,
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.driver = {
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.name = KBUILD_MODNAME,
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.acpi_match_table = cxl_acpi_ids,
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},
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};
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module_platform_driver(cxl_acpi_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_IMPORT_NS(CXL);
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MODULE_IMPORT_NS(ACPI);
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