mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-26 10:49:33 +00:00
![Bryan Wu](/assets/img/avatar_default.png)
This is the driver for latest Blackfin on-chip nand flash controller - use nand_chip and mtd_info common nand driver interface - provide both PIO and dma operation - compiled with ezkit bf548 configuration - use hardware 1-bit ECC - tested with YAFFS2 and can mount YAFFS2 filesystem as rootfs ChangeLog from try#1 - use hweight32() instead of count_bits() - replace bf54x with bf5xx and BF54X with BF5XX - compare against plat->page_size in 2 cases when enable hardware ECC ChangeLog from try#2 - passed nand_test suites - use cpu_relax() instead of busy wait loop - some coding style issue pointed out by Andrew Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: David Woodhouse <dwmw2@infradead.org>
74 lines
1.9 KiB
C
74 lines
1.9 KiB
C
/*
|
|
* file: include/asm-blackfin/mach-bf548/dma.h
|
|
* based on:
|
|
* author:
|
|
*
|
|
* created:
|
|
* description:
|
|
* system mmr register map
|
|
* rev:
|
|
*
|
|
* modified:
|
|
*
|
|
*
|
|
* bugs: enter bugs at http://blackfin.uclinux.org/
|
|
*
|
|
* this program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the gnu general public license as published by
|
|
* the free software foundation; either version 2, or (at your option)
|
|
* any later version.
|
|
*
|
|
* this program is distributed in the hope that it will be useful,
|
|
* but without any warranty; without even the implied warranty of
|
|
* merchantability or fitness for a particular purpose. see the
|
|
* gnu general public license for more details.
|
|
*
|
|
* you should have received a copy of the gnu general public license
|
|
* along with this program; see the file copying.
|
|
* if not, write to the free software foundation,
|
|
* 59 temple place - suite 330, boston, ma 02111-1307, usa.
|
|
*/
|
|
|
|
#ifndef _MACH_DMA_H_
|
|
#define _MACH_DMA_H_
|
|
|
|
#define CH_SPORT0_RX 0
|
|
#define CH_SPORT0_TX 1
|
|
#define CH_SPORT1_RX 2
|
|
#define CH_SPORT1_TX 3
|
|
#define CH_SPI0 4
|
|
#define CH_SPI1 5
|
|
#define CH_UART0_RX 6
|
|
#define CH_UART0_TX 7
|
|
#define CH_UART1_RX 8
|
|
#define CH_UART1_TX 9
|
|
#define CH_ATAPI_RX 10
|
|
#define CH_ATAPI_TX 11
|
|
#define CH_EPPI0 12
|
|
#define CH_EPPI1 13
|
|
#define CH_EPPI2 14
|
|
#define CH_PIXC_IMAGE 15
|
|
#define CH_PIXC_OVERLAY 16
|
|
#define CH_PIXC_OUTPUT 17
|
|
#define CH_SPORT2_RX 18
|
|
#define CH_SPORT2_TX 19
|
|
#define CH_SPORT3_RX 20
|
|
#define CH_SPORT3_TX 21
|
|
#define CH_SDH 22
|
|
#define CH_NFC 22
|
|
#define CH_SPI2 23
|
|
|
|
#define CH_MEM_STREAM0_DEST 24
|
|
#define CH_MEM_STREAM0_SRC 25
|
|
#define CH_MEM_STREAM1_DEST 26
|
|
#define CH_MEM_STREAM1_SRC 27
|
|
#define CH_MEM_STREAM2_DEST 28
|
|
#define CH_MEM_STREAM2_SRC 29
|
|
#define CH_MEM_STREAM3_DEST 30
|
|
#define CH_MEM_STREAM3_SRC 31
|
|
|
|
#define MAX_BLACKFIN_DMA_CHANNEL 32
|
|
|
|
extern int channel2irq(unsigned int channel);
|
|
extern struct dma_register *base_addr[];
|
|
#endif
|