Greentime Hu 20d2292754 riscv: make sure the cores stay looping in .Lsecondary_park ... The code in secondary_park is currently placed in the .init section. The kernel reclaims and clears this code when it finishes booting. That causes the cores parked in it to go to somewhere unpredictable, so we move this function out of init to make sure the cores stay looping there. The instruction bgeu a0, t0, .Lsecondary_park may have "a relocation truncated to fit" issue during linking time. It is because that sections are too far to jump. Let's use tail to jump to the .Lsecondary_park. Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Reviewed-by: Anup Patel <anup.patel@sifive.com> Cc: Andreas Schwab <schwab@suse.de> Cc: stable@vger.kernel.org Fixes: 76d2a0493a ("RISC-V: Init and Halt Code") Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>		2020-01-15 18:07:54 -08:00
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boot	riscv: dts: Add DT support for SiFive L2 cache controller	2020-01-03 00:56:23 -08:00
configs	Merge branch 'next/defconfig-add-debug' into for-next	2019-11-22 18:59:23 -08:00
include	riscv: move sifive_l2_cache.h to include/soc	2020-01-12 10:12:44 -08:00
kernel	riscv: make sure the cores stay looping in .Lsecondary_park	2020-01-15 18:07:54 -08:00
lib	riscv: fix compile failure with EXPORT_SYMBOL() & !MMU	2019-12-27 21:44:36 -08:00
mm	riscv: mm: use __pa_symbol for kernel symbols	2020-01-03 00:33:34 -08:00
net	bpf, riscv: Limit to 33 tail calls	2019-12-11 13:57:17 +01:00
Kbuild	riscv: add arch/riscv/Kbuild	2019-08-30 17:34:00 -07:00
Kconfig	riscv: Implement copy_thread_tls	2020-01-07 13:31:23 +01:00
Kconfig.debug	RISC-V: Remove EARLY_PRINTK support	2018-12-17 10:23:46 -08:00
Kconfig.socs	riscv: only select serial sifive if TTY is enabled	2019-12-08 20:29:01 -08:00
Makefile	riscv: provide a flat image loader	2019-11-17 15:17:39 -08:00