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6213f70e7c
Consolidating the "pen_release" stuff amongst the various SoC implementations gives credence to having a CPU holding pen for secondary CPUs. However, this is far from the truth. Many SoC implementations cargo-cult copied various bits of the pen release implementation from the initial Realview/Versatile Express implementation without understanding what it was or why it existed. The reason it existed is because these are _development_ platforms, and some board firmware is unable to individually control the startup of secondary CPUs. Moreover, they do not have a way to power down or reset secondary CPUs for hot-unplug. Hence, the pen_release implementation was designed for ARM Ltd's development platforms to provide a working implementation, even though it is very far from what is required. It was decided a while back to reduce the duplication by consolidating the "pen_release" variable, but this only made the situation worse - we have ended up with several implementations that read this variable but do not write it - again, showing the cargo-cult mentality at work, lack of proper review of new code, and in some cases a lack of testing. While it would be preferable to remove pen_release entirely from the kernel, this is not possible without help from the SoC maintainers, which seems to be lacking. However, I want to remove pen_release from arch code to remove the credence that having it gives. This patch removes pen_release from the arch code entirely, adding private per-SoC definitions for it instead, and explicitly stating that write_pen_release() is cargo-cult copied and should not be copied any further. Rename write_pen_release() in a similar fashion as well. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
39 lines
847 B
ArmAsm
39 lines
847 B
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Cloned from linux/arch/arm/mach-realview/headsmp.S
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*
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* Copyright (c) 2003 ARM Limited
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* All Rights Reserved
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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/*
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* exynos4 specific entry point for secondary CPUs. This provides
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* a "holding pen" into which all secondary cores are held until we're
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* ready for them to initialise.
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*/
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ENTRY(exynos4_secondary_startup)
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ARM_BE8(setend be)
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mrc p15, 0, r0, c0, c0, 5
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and r0, r0, #15
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adr r4, 1f
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ldmia r4, {r5, r6}
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sub r4, r4, r5
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add r6, r6, r4
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pen: ldr r7, [r6]
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cmp r7, r0
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bne pen
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/*
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* we've been released from the holding pen: secondary_stack
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* should now contain the SVC stack for this core
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*/
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b secondary_startup
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ENDPROC(exynos4_secondary_startup)
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.align 2
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1: .long .
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.long exynos_pen_release
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