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![Carlos Leija](/assets/img/avatar_default.png)
We need to add a dummy smc call to the cpuidle wakeup path to force the ROM code to save the return address after MMU is enabled again. This is needed to prevent random hangs on secure devices like droid4. Otherwise the system will eventually hang when entering deeper SoC idle states with the core and mpu domains in open-switch retention (OSWR). The hang happens as the ROM code tries to use the earlier physical return address set by omap-headsmp.S with MMU off while waking up CPU1 again. The hangs started happening in theory already with commitcaf8c87d7f
("ARM: OMAP2+: Allow core oswr for omap4"), but in practise the issue went unnoticed as various drivers were often blocking any deeper idle states with hardware autoidle features. This patch is based on an earlier TI Linux kernel tree commit 92f0b3028d9e ("OMAP4: PM: update ROM return address for OSWR and OFF") written by Carlos Leija <cileija@ti.com>, Praneeth Bajjuri <praneeth@ti.com>, and Bryan Buckley <bryan.buckley@ti.com>. A later version of the patch was updated to use CPU_PM notifiers by Tero Kristo <t-kristo@ti.com>. Signed-off-by: Carlos Leija <cileija@ti.com> Signed-off-by: Praneeth Bajjuri <praneeth@ti.com> Signed-off-by: Bryan Buckley <bryan.buckley@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Fixes:caf8c87d7f
("ARM: OMAP2+: Allow core oswr for omap4") Reported-by: Carl Philipp Klemm <philipp@uvos.xyz> Reported-by: Merlijn Wajer <merlijn@wizzup.org> Cc: Ivan Jelincic <parazyd@dyne.org> Cc: Pavel Machek <pavel@ucw.cz> Cc: Sebastian Reichel <sre@kernel.org> Cc: Tero Kristo <kristo@kernel.org> [tony@atomide.com: updated to apply, updated description] Signed-off-by: Tony Lindgren <tony@atomide.com>
254 lines
5.9 KiB
C
254 lines
5.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* OMAP Secure API infrastructure.
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*
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* Copyright (C) 2011 Texas Instruments, Inc.
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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* Copyright (C) 2012 Ivaylo Dimitrov <freemangordon@abv.bg>
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* Copyright (C) 2013 Pali Rohár <pali@kernel.org>
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*/
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#include <linux/arm-smccc.h>
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#include <linux/cpu_pm.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/memblock.h>
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#include <linux/of.h>
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#include <asm/cacheflush.h>
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#include <asm/memblock.h>
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#include "common.h"
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#include "omap-secure.h"
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#include "soc.h"
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static phys_addr_t omap_secure_memblock_base;
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bool optee_available;
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#define OMAP_SIP_SMC_STD_CALL_VAL(func_num) \
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ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_32, \
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ARM_SMCCC_OWNER_SIP, (func_num))
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static void __init omap_optee_init_check(void)
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{
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struct device_node *np;
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/*
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* We only check that the OP-TEE node is present and available. The
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* OP-TEE kernel driver is not needed for the type of interaction made
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* with OP-TEE here so the driver's status is not checked.
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*/
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np = of_find_node_by_path("/firmware/optee");
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if (np && of_device_is_available(np))
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optee_available = true;
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of_node_put(np);
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}
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/**
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* omap_sec_dispatcher: Routine to dispatch low power secure
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* service routines
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* @idx: The HAL API index
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* @flag: The flag indicating criticality of operation
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* @nargs: Number of valid arguments out of four.
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* @arg1, arg2, arg3 args4: Parameters passed to secure API
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*
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* Return the non-zero error value on failure.
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*/
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u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2,
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u32 arg3, u32 arg4)
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{
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u32 ret;
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u32 param[5];
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param[0] = nargs;
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param[1] = arg1;
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param[2] = arg2;
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param[3] = arg3;
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param[4] = arg4;
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/*
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* Secure API needs physical address
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* pointer for the parameters
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*/
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flush_cache_all();
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outer_clean_range(__pa(param), __pa(param + 5));
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ret = omap_smc2(idx, flag, __pa(param));
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return ret;
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}
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void omap_smccc_smc(u32 fn, u32 arg)
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{
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struct arm_smccc_res res;
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arm_smccc_smc(OMAP_SIP_SMC_STD_CALL_VAL(fn), arg,
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0, 0, 0, 0, 0, 0, &res);
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WARN(res.a0, "Secure function call 0x%08x failed\n", fn);
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}
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void omap_smc1(u32 fn, u32 arg)
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{
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/*
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* If this platform has OP-TEE installed we use ARM SMC calls
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* otherwise fall back to the OMAP ROM style calls.
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*/
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if (optee_available)
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omap_smccc_smc(fn, arg);
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else
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_omap_smc1(fn, arg);
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}
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/* Allocate the memory to save secure ram */
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int __init omap_secure_ram_reserve_memblock(void)
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{
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u32 size = OMAP_SECURE_RAM_STORAGE;
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size = ALIGN(size, SECTION_SIZE);
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omap_secure_memblock_base = arm_memblock_steal(size, SECTION_SIZE);
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return 0;
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}
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phys_addr_t omap_secure_ram_mempool_base(void)
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{
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return omap_secure_memblock_base;
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}
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#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
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u32 omap3_save_secure_ram(void __iomem *addr, int size)
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{
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u32 ret;
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u32 param[5];
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if (size != OMAP3_SAVE_SECURE_RAM_SZ)
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return OMAP3_SAVE_SECURE_RAM_SZ;
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param[0] = 4; /* Number of arguments */
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param[1] = __pa(addr); /* Physical address for saving */
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param[2] = 0;
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param[3] = 1;
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param[4] = 1;
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ret = save_secure_ram_context(__pa(param));
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return ret;
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}
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#endif
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/**
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* rx51_secure_dispatcher: Routine to dispatch secure PPA API calls
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* @idx: The PPA API index
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* @process: Process ID
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* @flag: The flag indicating criticality of operation
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* @nargs: Number of valid arguments out of four.
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* @arg1, arg2, arg3 args4: Parameters passed to secure API
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*
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* Return the non-zero error value on failure.
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*
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* NOTE: rx51_secure_dispatcher differs from omap_secure_dispatcher because
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* it calling omap_smc3() instead omap_smc2() and param[0] is nargs+1
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*/
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u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs,
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u32 arg1, u32 arg2, u32 arg3, u32 arg4)
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{
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u32 ret;
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u32 param[5];
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param[0] = nargs+1; /* RX-51 needs number of arguments + 1 */
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param[1] = arg1;
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param[2] = arg2;
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param[3] = arg3;
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param[4] = arg4;
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/*
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* Secure API needs physical address
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* pointer for the parameters
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*/
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local_irq_disable();
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local_fiq_disable();
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flush_cache_all();
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outer_clean_range(__pa(param), __pa(param + 5));
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ret = omap_smc3(idx, process, flag, __pa(param));
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flush_cache_all();
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local_fiq_enable();
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local_irq_enable();
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return ret;
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}
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/**
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* rx51_secure_update_aux_cr: Routine to modify the contents of Auxiliary Control Register
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* @set_bits: bits to set in ACR
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* @clr_bits: bits to clear in ACR
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*
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* Return the non-zero error value on failure.
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*/
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u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits)
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{
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u32 acr;
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/* Read ACR */
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asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
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acr &= ~clear_bits;
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acr |= set_bits;
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return rx51_secure_dispatcher(RX51_PPA_WRITE_ACR,
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0,
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FLAG_START_CRITICAL,
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1, acr, 0, 0, 0);
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}
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/**
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* rx51_secure_rng_call: Routine for HW random generator
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*/
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u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag)
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{
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return rx51_secure_dispatcher(RX51_PPA_HWRNG,
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0,
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NO_FLAG,
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3, ptr, count, flag, 0);
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}
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void __init omap_secure_init(void)
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{
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omap_optee_init_check();
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}
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/*
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* Dummy dispatcher call after core OSWR and MPU off. Updates the ROM return
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* address after MMU has been re-enabled after CPU1 has been woken up again.
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* Otherwise the ROM code will attempt to use the earlier physical return
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* address that got set with MMU off when waking up CPU1. Only used on secure
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* devices.
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*/
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static int cpu_notifier(struct notifier_block *nb, unsigned long cmd, void *v)
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{
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switch (cmd) {
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case CPU_CLUSTER_PM_EXIT:
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omap_secure_dispatcher(OMAP4_PPA_SERVICE_0,
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FLAG_START_CRITICAL,
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0, 0, 0, 0, 0);
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break;
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default:
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break;
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}
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return NOTIFY_OK;
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}
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static struct notifier_block secure_notifier_block = {
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.notifier_call = cpu_notifier,
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};
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static int __init secure_pm_init(void)
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{
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if (omap_type() == OMAP2_DEVICE_TYPE_GP || !soc_is_omap44xx())
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return 0;
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cpu_pm_register_notifier(&secure_notifier_block);
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return 0;
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}
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omap_arch_initcall(secure_pm_init);
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