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Almost all SoC code changes this time are for the TI OMAP platform, which continues its decade-long quest to move from describing a complex SoC in code to device tree. Aside from this, the Uniphier platform has a new maintainer and some platforms have minor bugfixes and cleanups that were not urgent enough for v5.12. Signed-off-by: Arnd Bergmann <arnd@arndb.de> -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmCC2JoACgkQmmx57+YA GNk2jg/9HPrMBjoxNMEynsN066Dnc3AVBG8veYAigS0mJuMX3HzUqp+RNn5YxEak 0SKWgocjawi5MjtuCRmM/BO0SY4wPUMOxnqx/AE4q3u6VVpfx+XJu+1bywAx7UFC FnqstmqFAfJDLJUe4Pfv4SuXRJYyGKBoEdRK9Xr13qSstQ1gm4ccWbtRStWCcVvv f4J0gPK0dw99lgbCOLbrBMfz1zuxCwhILg+qZ0+WPl9NNfxurQ2+/Cj/8P/L0IH+ BoiZ5NaISWnvlBWaSTh6P7d3omhbA149CPjybUy2b/s84oNHdm7XLpwymVp941zt sM3gBIi7UDKMfXUrjWDZAXY06MZa/62BLCHQ2Fx+A1ve9TC0AqmSmUxhB4Z8xXs2 3U97kZnTAPX9Scno9k7eDXbVXKVzlDL8zdZtGvY56x/EiAiPSJaTcaU6puNgdF9z 7IPFKdpMbePcxHN03dC17B4HYVoSTp2gCadOSRSrBmVjAoswzYKoAOHrzibCwUzI knbsShhJe/BtxvLJ7e/hq0YZBTTZXUcX/3Iuw6C+j+9l9Cod/JhYOoHQM7gvqHv6 JRz0Wt9IrMhYBMYlf0g8zHZa7IUDAq7k6x8XwLjK/M/WdeS2tI3+Cmt5ePhlgZVb eBPzikxcvglDojE7zTkBeC/+jlpolWQ6UfRnptSvkof1DWVPkiE= =YFEX -----END PGP SIGNATURE----- Merge tag 'arm-soc-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC updates from Arnd Bergmann: "Almost all SoC code changes this time are for the TI OMAP platform, which continues its decade-long quest to move from describing a complex SoC in code to device tree. Aside from this, the Uniphier platform has a new maintainer and some platforms have minor bugfixes and cleanups that were not urgent enough for v5.12" * tag 'arm-soc-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (96 commits) MAINTAINERS: Update ARM/UniPhier SoCs maintainers and status mailmap: Update email address for Nicolas Saenz MAINTAINERS: Update BCM2711/BCM2335 maintainer's mail ARM: exynos: correct kernel doc in platsmp ARM: hisi: use the correct HiSilicon copyright ARM: ux500: make ux500_cpu_die static ARM: s3c: Use pwm_get() in favour of pwm_request() in RX1950 ARM: OMAP1: fix incorrect kernel-doc comment syntax in file ARM: OMAP2+: fix incorrect kernel-doc comment syntax in file ARM: OMAP2+: Use DEFINE_SPINLOCK() for spinlock ARM: at91: pm: Move prototypes to mutually included header ARM: OMAP2+: use true and false for bool variable ARM: OMAP2+: add missing call to of_node_put() ARM: OMAP2+: Replace DEFINE_SIMPLE_ATTRIBUTE with DEFINE_DEBUGFS_ATTRIBUTE ARM: imx: Kconfig: Fix typo in help ARM: mach-imx: Fix a spelling in the file pm-imx5.c bus: ti-sysc: Warn about old dtb for dra7 and omap4/5 ARM: OMAP2+: Stop building legacy code for dra7 and omap4/5 ARM: OMAP2+: Drop legacy platform data for omap5 hwmod ARM: OMAP2+: Drop legacy platform data for omap5 l3 ...
223 lines
5.2 KiB
C
223 lines
5.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* OMAP3/OMAP4 smartreflex device file
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*
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* Author: Thara Gopinath <thara@ti.com>
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*
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* Based originally on code from smartreflex.c
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* Copyright (C) 2010 Texas Instruments, Inc.
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* Thara Gopinath <thara@ti.com>
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*
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* Copyright (C) 2008 Nokia Corporation
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* Kalle Jokiniemi
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*
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* Copyright (C) 2007 Texas Instruments, Inc.
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* Lesly A M <x0080970@ti.com>
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*/
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#include <linux/power/smartreflex.h>
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#include <linux/err.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include "soc.h"
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#include "omap_device.h"
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#include "voltage.h"
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#include "control.h"
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#include "pm.h"
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static bool sr_enable_on_init;
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/* Read EFUSE values from control registers for OMAP3430 */
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static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
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struct omap_sr_data *sr_data)
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{
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struct omap_sr_nvalue_table *nvalue_table;
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int i, j, count = 0;
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sr_data->nvalue_count = 0;
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sr_data->nvalue_table = NULL;
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while (volt_data[count].volt_nominal)
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count++;
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nvalue_table = kcalloc(count, sizeof(*nvalue_table), GFP_KERNEL);
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if (!nvalue_table)
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return;
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for (i = 0, j = 0; i < count; i++) {
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u32 v;
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/*
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* In OMAP4 the efuse registers are 24 bit aligned.
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* A readl_relaxed will fail for non-32 bit aligned address
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* and hence the 8-bit read and shift.
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*/
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if (cpu_is_omap44xx()) {
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u16 offset = volt_data[i].sr_efuse_offs;
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v = omap_ctrl_readb(offset) |
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omap_ctrl_readb(offset + 1) << 8 |
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omap_ctrl_readb(offset + 2) << 16;
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} else {
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v = omap_ctrl_readl(volt_data[i].sr_efuse_offs);
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}
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/*
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* Many OMAP SoCs don't have the eFuse values set.
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* For example, pretty much all OMAP3xxx before
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* ES3.something.
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*
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* XXX There needs to be some way for board files or
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* userspace to add these in.
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*/
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if (v == 0)
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continue;
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nvalue_table[j].nvalue = v;
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nvalue_table[j].efuse_offs = volt_data[i].sr_efuse_offs;
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nvalue_table[j].errminlimit = volt_data[i].sr_errminlimit;
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nvalue_table[j].volt_nominal = volt_data[i].volt_nominal;
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j++;
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}
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sr_data->nvalue_table = nvalue_table;
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sr_data->nvalue_count = j;
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}
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extern struct omap_sr_data omap_sr_pdata[];
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static int __init sr_init_by_name(const char *name, const char *voltdm)
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{
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struct omap_sr_data *sr_data = NULL;
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struct omap_volt_data *volt_data;
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static int i;
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if (!strncmp(name, "smartreflex_mpu_iva", 20) ||
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!strncmp(name, "smartreflex_mpu", 16))
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sr_data = &omap_sr_pdata[OMAP_SR_MPU];
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else if (!strncmp(name, "smartreflex_core", 17))
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sr_data = &omap_sr_pdata[OMAP_SR_CORE];
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else if (!strncmp(name, "smartreflex_iva", 16))
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sr_data = &omap_sr_pdata[OMAP_SR_IVA];
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if (!sr_data) {
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pr_err("%s: Unknown instance %s\n", __func__, name);
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return -EINVAL;
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}
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sr_data->name = name;
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if (cpu_is_omap343x())
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sr_data->ip_type = 1;
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else
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sr_data->ip_type = 2;
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sr_data->senn_mod = 0x1;
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sr_data->senp_mod = 0x1;
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if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
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sr_data->err_weight = OMAP3430_SR_ERRWEIGHT;
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sr_data->err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
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sr_data->accum_data = OMAP3430_SR_ACCUMDATA;
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if (!(strcmp(sr_data->name, "smartreflex_mpu"))) {
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sr_data->senn_avgweight = OMAP3430_SR1_SENNAVGWEIGHT;
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sr_data->senp_avgweight = OMAP3430_SR1_SENPAVGWEIGHT;
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} else {
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sr_data->senn_avgweight = OMAP3430_SR2_SENNAVGWEIGHT;
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sr_data->senp_avgweight = OMAP3430_SR2_SENPAVGWEIGHT;
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}
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}
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sr_data->voltdm = voltdm_lookup(voltdm);
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if (!sr_data->voltdm) {
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pr_err("%s: Unable to get voltage domain pointer for VDD %s\n",
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__func__, voltdm);
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goto exit;
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}
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omap_voltage_get_volttable(sr_data->voltdm, &volt_data);
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if (!volt_data) {
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pr_err("%s: No Voltage table registered for VDD%d\n",
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__func__, i + 1);
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goto exit;
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}
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sr_set_nvalues(volt_data, sr_data);
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sr_data->enable_on_init = sr_enable_on_init;
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exit:
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i++;
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return 0;
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}
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#ifdef CONFIG_OMAP_HWMOD
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static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
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{
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struct omap_smartreflex_dev_attr *sr_dev_attr;
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sr_dev_attr = (struct omap_smartreflex_dev_attr *)oh->dev_attr;
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if (!sr_dev_attr || !sr_dev_attr->sensor_voltdm_name) {
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pr_err("%s: No voltage domain specified for %s. Cannot initialize\n",
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__func__, oh->name);
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return 0;
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}
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return sr_init_by_name(oh->name, sr_dev_attr->sensor_voltdm_name);
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}
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#else
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static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
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{
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return -EINVAL;
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}
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#endif
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/*
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* API to be called from board files to enable smartreflex
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* autocompensation at init.
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*/
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void __init omap_enable_smartreflex_on_init(void)
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{
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sr_enable_on_init = true;
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}
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static const char * const omap4_sr_instances[] = {
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"mpu",
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"iva",
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"core",
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};
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static const char * const dra7_sr_instances[] = {
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"mpu",
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"core",
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};
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int __init omap_devinit_smartreflex(void)
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{
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const char * const *sr_inst = NULL;
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int i, nr_sr = 0;
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if (soc_is_omap44xx()) {
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sr_inst = omap4_sr_instances;
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nr_sr = ARRAY_SIZE(omap4_sr_instances);
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} else if (soc_is_dra7xx()) {
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sr_inst = dra7_sr_instances;
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nr_sr = ARRAY_SIZE(dra7_sr_instances);
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}
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if (nr_sr) {
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const char *name, *voltdm;
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for (i = 0; i < nr_sr; i++) {
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name = kasprintf(GFP_KERNEL, "smartreflex_%s", sr_inst[i]);
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voltdm = sr_inst[i];
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sr_init_by_name(name, voltdm);
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}
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return 0;
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}
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return omap_hwmod_for_each_by_class("smartreflex", sr_dev_init, NULL);
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}
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