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![afzal mohammed](/assets/img/avatar_default.png)
request_irq() is preferred over setup_irq(). Invocations of setup_irq() occur after memory allocators are ready. Per tglx[1], setup_irq() existed in olden days when allocators were not ready by the time early interrupts were initialized. Hence replace setup_irq() by request_irq(). [1] https://lkml.kernel.org/r/alpine.DEB.2.20.1710191609480.1971@nanos Link: https://lore.kernel.org/r/20200327124406.4123-1-afzal.mohd.ma@gmail.com Signed-off-by: afzal mohammed <afzal.mohd.ma@gmail.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
251 lines
5.7 KiB
C
251 lines
5.7 KiB
C
/*
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* arch/arm/plat-spear/time.c
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*
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* Copyright (C) 2010 ST Microelectronics
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* Shiraz Hashim<shiraz.linux.kernel@gmail.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/time.h>
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#include <linux/irq.h>
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#include <asm/mach/time.h>
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#include "generic.h"
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/*
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* We would use TIMER0 and TIMER1 as clockevent and clocksource.
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* Timer0 and Timer1 both belong to same gpt block in cpu subbsystem. Further
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* they share same functional clock. Any change in one's functional clock will
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* also affect other timer.
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*/
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#define CLKEVT 0 /* gpt0, channel0 as clockevent */
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#define CLKSRC 1 /* gpt0, channel1 as clocksource */
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/* Register offsets, x is channel number */
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#define CR(x) ((x) * 0x80 + 0x80)
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#define IR(x) ((x) * 0x80 + 0x84)
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#define LOAD(x) ((x) * 0x80 + 0x88)
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#define COUNT(x) ((x) * 0x80 + 0x8C)
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/* Reg bit definitions */
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#define CTRL_INT_ENABLE 0x0100
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#define CTRL_ENABLE 0x0020
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#define CTRL_ONE_SHOT 0x0010
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#define CTRL_PRESCALER1 0x0
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#define CTRL_PRESCALER2 0x1
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#define CTRL_PRESCALER4 0x2
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#define CTRL_PRESCALER8 0x3
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#define CTRL_PRESCALER16 0x4
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#define CTRL_PRESCALER32 0x5
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#define CTRL_PRESCALER64 0x6
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#define CTRL_PRESCALER128 0x7
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#define CTRL_PRESCALER256 0x8
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#define INT_STATUS 0x1
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/*
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* Minimum clocksource/clockevent timer range in seconds
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*/
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#define SPEAR_MIN_RANGE 4
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static __iomem void *gpt_base;
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static struct clk *gpt_clk;
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static int clockevent_next_event(unsigned long evt,
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struct clock_event_device *clk_event_dev);
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static void __init spear_clocksource_init(void)
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{
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u32 tick_rate;
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u16 val;
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/* program the prescaler (/256)*/
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writew(CTRL_PRESCALER256, gpt_base + CR(CLKSRC));
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/* find out actual clock driving Timer */
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tick_rate = clk_get_rate(gpt_clk);
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tick_rate >>= CTRL_PRESCALER256;
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writew(0xFFFF, gpt_base + LOAD(CLKSRC));
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val = readw(gpt_base + CR(CLKSRC));
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val &= ~CTRL_ONE_SHOT; /* autoreload mode */
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val |= CTRL_ENABLE ;
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writew(val, gpt_base + CR(CLKSRC));
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/* register the clocksource */
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clocksource_mmio_init(gpt_base + COUNT(CLKSRC), "tmr1", tick_rate,
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200, 16, clocksource_mmio_readw_up);
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}
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static inline void timer_shutdown(struct clock_event_device *evt)
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{
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u16 val = readw(gpt_base + CR(CLKEVT));
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/* stop the timer */
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val &= ~CTRL_ENABLE;
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writew(val, gpt_base + CR(CLKEVT));
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}
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static int spear_shutdown(struct clock_event_device *evt)
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{
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timer_shutdown(evt);
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return 0;
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}
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static int spear_set_oneshot(struct clock_event_device *evt)
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{
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u16 val;
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/* stop the timer */
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timer_shutdown(evt);
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val = readw(gpt_base + CR(CLKEVT));
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val |= CTRL_ONE_SHOT;
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writew(val, gpt_base + CR(CLKEVT));
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return 0;
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}
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static int spear_set_periodic(struct clock_event_device *evt)
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{
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u32 period;
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u16 val;
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/* stop the timer */
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timer_shutdown(evt);
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period = clk_get_rate(gpt_clk) / HZ;
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period >>= CTRL_PRESCALER16;
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writew(period, gpt_base + LOAD(CLKEVT));
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val = readw(gpt_base + CR(CLKEVT));
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val &= ~CTRL_ONE_SHOT;
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val |= CTRL_ENABLE | CTRL_INT_ENABLE;
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writew(val, gpt_base + CR(CLKEVT));
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return 0;
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}
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static struct clock_event_device clkevt = {
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.name = "tmr0",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_state_shutdown = spear_shutdown,
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.set_state_periodic = spear_set_periodic,
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.set_state_oneshot = spear_set_oneshot,
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.tick_resume = spear_shutdown,
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.set_next_event = clockevent_next_event,
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.shift = 0, /* to be computed */
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};
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static int clockevent_next_event(unsigned long cycles,
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struct clock_event_device *clk_event_dev)
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{
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u16 val = readw(gpt_base + CR(CLKEVT));
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if (val & CTRL_ENABLE)
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writew(val & ~CTRL_ENABLE, gpt_base + CR(CLKEVT));
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writew(cycles, gpt_base + LOAD(CLKEVT));
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val |= CTRL_ENABLE | CTRL_INT_ENABLE;
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writew(val, gpt_base + CR(CLKEVT));
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return 0;
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}
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static irqreturn_t spear_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = &clkevt;
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writew(INT_STATUS, gpt_base + IR(CLKEVT));
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static void __init spear_clockevent_init(int irq)
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{
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u32 tick_rate;
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/* program the prescaler */
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writew(CTRL_PRESCALER16, gpt_base + CR(CLKEVT));
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tick_rate = clk_get_rate(gpt_clk);
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tick_rate >>= CTRL_PRESCALER16;
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clkevt.cpumask = cpumask_of(0);
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clockevents_config_and_register(&clkevt, tick_rate, 3, 0xfff0);
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if (request_irq(irq, spear_timer_interrupt, IRQF_TIMER, "timer", NULL))
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pr_err("Failed to request irq %d (timer)\n", irq);
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}
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static const struct of_device_id timer_of_match[] __initconst = {
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{ .compatible = "st,spear-timer", },
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{ },
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};
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void __init spear_setup_of_timer(void)
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{
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struct device_node *np;
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int irq, ret;
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np = of_find_matching_node(NULL, timer_of_match);
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if (!np) {
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pr_err("%s: No timer passed via DT\n", __func__);
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return;
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}
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irq = irq_of_parse_and_map(np, 0);
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if (!irq) {
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pr_err("%s: No irq passed for timer via DT\n", __func__);
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return;
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}
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gpt_base = of_iomap(np, 0);
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if (!gpt_base) {
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pr_err("%s: of iomap failed\n", __func__);
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return;
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}
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gpt_clk = clk_get_sys("gpt0", NULL);
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if (IS_ERR(gpt_clk)) {
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pr_err("%s:couldn't get clk for gpt\n", __func__);
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goto err_iomap;
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}
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ret = clk_prepare_enable(gpt_clk);
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if (ret < 0) {
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pr_err("%s:couldn't prepare-enable gpt clock\n", __func__);
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goto err_prepare_enable_clk;
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}
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spear_clockevent_init(irq);
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spear_clocksource_init();
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return;
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err_prepare_enable_clk:
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clk_put(gpt_clk);
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err_iomap:
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iounmap(gpt_base);
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}
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