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![Thomas Bogendoerfer](/assets/img/avatar_default.png)
KVM_GUEST is broken and unmaintained, so let's remove it. Reviewed-by: Huacai Chen <chenhuacai@kernel.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
341 lines
8.6 KiB
C
341 lines
8.6 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2007 MIPS Technologies, Inc.
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* Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
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*/
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/cpufreq.h>
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#include <linux/percpu.h>
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#include <linux/smp.h>
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#include <linux/irq.h>
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#include <asm/time.h>
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#include <asm/cevt-r4k.h>
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static int mips_next_event(unsigned long delta,
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struct clock_event_device *evt)
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{
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unsigned int cnt;
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int res;
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cnt = read_c0_count();
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cnt += delta;
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write_c0_compare(cnt);
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res = ((int)(read_c0_count() - cnt) >= 0) ? -ETIME : 0;
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return res;
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}
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/**
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* calculate_min_delta() - Calculate a good minimum delta for mips_next_event().
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*
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* Running under virtualisation can introduce overhead into mips_next_event() in
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* the form of hypervisor emulation of CP0_Count/CP0_Compare registers,
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* potentially with an unnatural frequency, which makes a fixed min_delta_ns
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* value inappropriate as it may be too small.
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*
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* It can also introduce occasional latency from the guest being descheduled.
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*
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* This function calculates a good minimum delta based roughly on the 75th
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* percentile of the time taken to do the mips_next_event() sequence, in order
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* to handle potentially higher overhead while also eliminating outliers due to
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* unpredictable hypervisor latency (which can be handled by retries).
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*
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* Return: An appropriate minimum delta for the clock event device.
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*/
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static unsigned int calculate_min_delta(void)
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{
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unsigned int cnt, i, j, k, l;
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unsigned int buf1[4], buf2[3];
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unsigned int min_delta;
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/*
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* Calculate the median of 5 75th percentiles of 5 samples of how long
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* it takes to set CP0_Compare = CP0_Count + delta.
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*/
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for (i = 0; i < 5; ++i) {
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for (j = 0; j < 5; ++j) {
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/*
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* This is like the code in mips_next_event(), and
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* directly measures the borderline "safe" delta.
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*/
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cnt = read_c0_count();
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write_c0_compare(cnt);
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cnt = read_c0_count() - cnt;
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/* Sorted insert into buf1 */
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for (k = 0; k < j; ++k) {
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if (cnt < buf1[k]) {
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l = min_t(unsigned int,
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j, ARRAY_SIZE(buf1) - 1);
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for (; l > k; --l)
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buf1[l] = buf1[l - 1];
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break;
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}
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}
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if (k < ARRAY_SIZE(buf1))
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buf1[k] = cnt;
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}
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/* Sorted insert of 75th percentile into buf2 */
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for (k = 0; k < i && k < ARRAY_SIZE(buf2); ++k) {
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if (buf1[ARRAY_SIZE(buf1) - 1] < buf2[k]) {
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l = min_t(unsigned int,
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i, ARRAY_SIZE(buf2) - 1);
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for (; l > k; --l)
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buf2[l] = buf2[l - 1];
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break;
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}
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}
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if (k < ARRAY_SIZE(buf2))
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buf2[k] = buf1[ARRAY_SIZE(buf1) - 1];
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}
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/* Use 2 * median of 75th percentiles */
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min_delta = buf2[ARRAY_SIZE(buf2) - 1] * 2;
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/* Don't go too low */
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if (min_delta < 0x300)
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min_delta = 0x300;
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pr_debug("%s: median 75th percentile=%#x, min_delta=%#x\n",
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__func__, buf2[ARRAY_SIZE(buf2) - 1], min_delta);
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return min_delta;
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}
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DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device);
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int cp0_timer_irq_installed;
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/*
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* Possibly handle a performance counter interrupt.
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* Return true if the timer interrupt should not be checked
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*/
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static inline int handle_perf_irq(int r2)
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{
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/*
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* The performance counter overflow interrupt may be shared with the
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* timer interrupt (cp0_perfcount_irq < 0). If it is and a
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* performance counter has overflowed (perf_irq() == IRQ_HANDLED)
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* and we can't reliably determine if a counter interrupt has also
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* happened (!r2) then don't check for a timer interrupt.
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*/
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return (cp0_perfcount_irq < 0) &&
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perf_irq() == IRQ_HANDLED &&
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!r2;
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}
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irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
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{
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const int r2 = cpu_has_mips_r2_r6;
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struct clock_event_device *cd;
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int cpu = smp_processor_id();
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/*
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* Suckage alert:
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* Before R2 of the architecture there was no way to see if a
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* performance counter interrupt was pending, so we have to run
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* the performance counter interrupt handler anyway.
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*/
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if (handle_perf_irq(r2))
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return IRQ_HANDLED;
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/*
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* The same applies to performance counter interrupts. But with the
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* above we now know that the reason we got here must be a timer
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* interrupt. Being the paranoiacs we are we check anyway.
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*/
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if (!r2 || (read_c0_cause() & CAUSEF_TI)) {
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/* Clear Count/Compare Interrupt */
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write_c0_compare(read_c0_compare());
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cd = &per_cpu(mips_clockevent_device, cpu);
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cd->event_handler(cd);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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struct irqaction c0_compare_irqaction = {
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.handler = c0_compare_interrupt,
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/*
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* IRQF_SHARED: The timer interrupt may be shared with other interrupts
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* such as perf counter and FDC interrupts.
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*/
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.flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED,
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.name = "timer",
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};
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void mips_event_handler(struct clock_event_device *dev)
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{
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}
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/*
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* FIXME: This doesn't hold for the relocated E9000 compare interrupt.
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*/
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static int c0_compare_int_pending(void)
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{
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/* When cpu_has_mips_r2, this checks Cause.TI instead of Cause.IP7 */
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return (read_c0_cause() >> cp0_compare_irq_shift) & (1ul << CAUSEB_IP);
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}
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/*
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* Compare interrupt can be routed and latched outside the core,
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* so wait up to worst case number of cycle counter ticks for timer interrupt
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* changes to propagate to the cause register.
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*/
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#define COMPARE_INT_SEEN_TICKS 50
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int c0_compare_int_usable(void)
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{
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unsigned int delta;
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unsigned int cnt;
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/*
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* IP7 already pending? Try to clear it by acking the timer.
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*/
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if (c0_compare_int_pending()) {
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cnt = read_c0_count();
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write_c0_compare(cnt);
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back_to_back_c0_hazard();
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while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS))
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if (!c0_compare_int_pending())
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break;
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if (c0_compare_int_pending())
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return 0;
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}
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for (delta = 0x10; delta <= 0x400000; delta <<= 1) {
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cnt = read_c0_count();
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cnt += delta;
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write_c0_compare(cnt);
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back_to_back_c0_hazard();
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if ((int)(read_c0_count() - cnt) < 0)
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break;
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/* increase delta if the timer was already expired */
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}
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while ((int)(read_c0_count() - cnt) <= 0)
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; /* Wait for expiry */
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while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS))
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if (c0_compare_int_pending())
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break;
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if (!c0_compare_int_pending())
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return 0;
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cnt = read_c0_count();
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write_c0_compare(cnt);
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back_to_back_c0_hazard();
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while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS))
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if (!c0_compare_int_pending())
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break;
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if (c0_compare_int_pending())
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return 0;
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/*
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* Feels like a real count / compare timer.
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*/
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return 1;
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}
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unsigned int __weak get_c0_compare_int(void)
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{
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return MIPS_CPU_IRQ_BASE + cp0_compare_irq;
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}
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#ifdef CONFIG_CPU_FREQ
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static unsigned long mips_ref_freq;
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static int r4k_cpufreq_callback(struct notifier_block *nb,
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unsigned long val, void *data)
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{
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struct cpufreq_freqs *freq = data;
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struct clock_event_device *cd;
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unsigned long rate;
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int cpu;
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if (!mips_ref_freq)
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mips_ref_freq = freq->old;
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if (val == CPUFREQ_POSTCHANGE) {
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rate = cpufreq_scale(mips_hpt_frequency, mips_ref_freq,
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freq->new);
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for_each_cpu(cpu, freq->policy->cpus) {
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cd = &per_cpu(mips_clockevent_device, cpu);
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clockevents_update_freq(cd, rate);
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}
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}
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return 0;
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}
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static struct notifier_block r4k_cpufreq_notifier = {
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.notifier_call = r4k_cpufreq_callback,
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};
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static int __init r4k_register_cpufreq_notifier(void)
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{
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return cpufreq_register_notifier(&r4k_cpufreq_notifier,
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CPUFREQ_TRANSITION_NOTIFIER);
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}
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core_initcall(r4k_register_cpufreq_notifier);
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#endif /* !CONFIG_CPU_FREQ */
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int r4k_clockevent_init(void)
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{
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unsigned long flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED;
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unsigned int cpu = smp_processor_id();
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struct clock_event_device *cd;
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unsigned int irq, min_delta;
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if (!cpu_has_counter || !mips_hpt_frequency)
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return -ENXIO;
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if (!c0_compare_int_usable())
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return -ENXIO;
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/*
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* With vectored interrupts things are getting platform specific.
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* get_c0_compare_int is a hook to allow a platform to return the
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* interrupt number of its liking.
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*/
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irq = get_c0_compare_int();
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cd = &per_cpu(mips_clockevent_device, cpu);
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cd->name = "MIPS";
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cd->features = CLOCK_EVT_FEAT_ONESHOT |
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CLOCK_EVT_FEAT_C3STOP |
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CLOCK_EVT_FEAT_PERCPU;
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min_delta = calculate_min_delta();
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cd->rating = 300;
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cd->irq = irq;
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cd->cpumask = cpumask_of(cpu);
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cd->set_next_event = mips_next_event;
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cd->event_handler = mips_event_handler;
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clockevents_config_and_register(cd, mips_hpt_frequency, min_delta, 0x7fffffff);
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if (cp0_timer_irq_installed)
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return 0;
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cp0_timer_irq_installed = 1;
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if (request_irq(irq, c0_compare_interrupt, flags, "timer",
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c0_compare_interrupt))
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pr_err("Failed to request irq %d (timer)\n", irq);
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return 0;
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}
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