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c7b5fd6faa
We'd like all architectures to convert to ARCH_ATOMIC, as once all
architectures are converted it will be possible to make significant
cleanups to the atomics headers, and this will make it much easier to
generically enable atomic functionality (e.g. debug logic in the
instrumented wrappers).
As a step towards that, this patch migrates mips to ARCH_ATOMIC. The
arch code provides arch_{atomic,atomic64,xchg,cmpxchg}*(), and common
code wraps these with optional instrumentation to provide the regular
functions.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Boqun Feng <boqun.feng@gmail.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lore.kernel.org/r/20210525140232.53872-23-mark.rutland@arm.com
104 lines
2.7 KiB
C
104 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2017 Imagination Technologies
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* Author: Paul Burton <paul.burton@mips.com>
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*/
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#include <linux/bitops.h>
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#include <asm/cmpxchg.h>
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unsigned long __xchg_small(volatile void *ptr, unsigned long val, unsigned int size)
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{
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u32 old32, new32, load32, mask;
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volatile u32 *ptr32;
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unsigned int shift;
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/* Check that ptr is naturally aligned */
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WARN_ON((unsigned long)ptr & (size - 1));
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/* Mask value to the correct size. */
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mask = GENMASK((size * BITS_PER_BYTE) - 1, 0);
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val &= mask;
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/*
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* Calculate a shift & mask that correspond to the value we wish to
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* exchange within the naturally aligned 4 byte integerthat includes
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* it.
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*/
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shift = (unsigned long)ptr & 0x3;
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if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
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shift ^= sizeof(u32) - size;
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shift *= BITS_PER_BYTE;
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mask <<= shift;
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/*
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* Calculate a pointer to the naturally aligned 4 byte integer that
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* includes our byte of interest, and load its value.
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*/
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ptr32 = (volatile u32 *)((unsigned long)ptr & ~0x3);
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load32 = *ptr32;
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do {
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old32 = load32;
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new32 = (load32 & ~mask) | (val << shift);
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load32 = arch_cmpxchg(ptr32, old32, new32);
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} while (load32 != old32);
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return (load32 & mask) >> shift;
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}
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unsigned long __cmpxchg_small(volatile void *ptr, unsigned long old,
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unsigned long new, unsigned int size)
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{
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u32 mask, old32, new32, load32, load;
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volatile u32 *ptr32;
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unsigned int shift;
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/* Check that ptr is naturally aligned */
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WARN_ON((unsigned long)ptr & (size - 1));
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/* Mask inputs to the correct size. */
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mask = GENMASK((size * BITS_PER_BYTE) - 1, 0);
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old &= mask;
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new &= mask;
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/*
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* Calculate a shift & mask that correspond to the value we wish to
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* compare & exchange within the naturally aligned 4 byte integer
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* that includes it.
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*/
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shift = (unsigned long)ptr & 0x3;
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if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
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shift ^= sizeof(u32) - size;
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shift *= BITS_PER_BYTE;
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mask <<= shift;
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/*
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* Calculate a pointer to the naturally aligned 4 byte integer that
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* includes our byte of interest, and load its value.
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*/
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ptr32 = (volatile u32 *)((unsigned long)ptr & ~0x3);
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load32 = *ptr32;
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while (true) {
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/*
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* Ensure the byte we want to exchange matches the expected
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* old value, and if not then bail.
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*/
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load = (load32 & mask) >> shift;
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if (load != old)
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return load;
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/*
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* Calculate the old & new values of the naturally aligned
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* 4 byte integer that include the byte we want to exchange.
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* Attempt to exchange the old value for the new value, and
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* return if we succeed.
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*/
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old32 = (load32 & ~mask) | (old << shift);
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new32 = (load32 & ~mask) | (new << shift);
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load32 = arch_cmpxchg(ptr32, old32, new32);
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if (load32 == old32)
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return old;
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}
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}
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