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![Thomas Bogendoerfer](/assets/img/avatar_default.png)
BMIPS is one of the few platforms that do change the exception base. After commit2dcb396454
("memblock: do not start bottom-up allocations with kernel_end") we started seeing BMIPS boards fail to boot with the built-in FDT being corrupted. Before the cited commit, early allocations would be in the [kernel_end, RAM_END] range, but after commit they would be within [RAM_START + PAGE_SIZE, RAM_END]. The custom exception base handler that is installed by bmips_ebase_setup() done for BMIPS5000 CPUs ends-up trampling on the memory region allocated by unflatten_and_copy_device_tree() thus corrupting the FDT used by the kernel. To fix this, we need to perform an early reservation of the custom exception space. Additional we reserve the first 4k (1k for R3k) for either normal exception vector space (legacy CPUs) or special vectors like cache exceptions. Huge thanks to Serge for analysing and proposing a solution to this issue. Fixes:2dcb396454
("memblock: do not start bottom-up allocations with kernel_end") Reported-by: Kamal Dasu <kdasu.kdev@gmail.com> Debugged-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Acked-by: Mike Rapoport <rppt@linux.ibm.com> Tested-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Serge Semin <fancer.lancer@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
174 lines
4.1 KiB
C
174 lines
4.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Processor capabilities determination functions.
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*
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* Copyright (C) xxxx the Anonymous
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* Copyright (C) 1994 - 2006 Ralf Baechle
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* Copyright (C) 2003, 2004 Maciej W. Rozycki
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* Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/ptrace.h>
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#include <linux/smp.h>
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#include <linux/stddef.h>
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#include <linux/export.h>
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#include <asm/bugs.h>
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#include <asm/cpu.h>
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#include <asm/cpu-features.h>
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#include <asm/cpu-type.h>
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#include <asm/fpu.h>
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#include <asm/mipsregs.h>
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#include <asm/elf.h>
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#include <asm/traps.h>
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#include "fpu-probe.h"
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/* Hardware capabilities */
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unsigned int elf_hwcap __read_mostly;
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EXPORT_SYMBOL_GPL(elf_hwcap);
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void __init check_bugs32(void)
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{
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}
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/*
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* Probe whether cpu has config register by trying to play with
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* alternate cache bit and see whether it matters.
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* It's used by cpu_probe to distinguish between R3000A and R3081.
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*/
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static inline int cpu_has_confreg(void)
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{
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#ifdef CONFIG_CPU_R3000
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extern unsigned long r3k_cache_size(unsigned long);
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unsigned long size1, size2;
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unsigned long cfg = read_c0_conf();
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size1 = r3k_cache_size(ST0_ISC);
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write_c0_conf(cfg ^ R30XX_CONF_AC);
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size2 = r3k_cache_size(ST0_ISC);
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write_c0_conf(cfg);
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return size1 != size2;
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#else
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return 0;
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#endif
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}
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static inline void set_elf_platform(int cpu, const char *plat)
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{
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if (cpu == 0)
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__elf_platform = plat;
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}
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const char *__cpu_name[NR_CPUS];
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const char *__elf_platform;
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const char *__elf_base_platform;
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void cpu_probe(void)
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{
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struct cpuinfo_mips *c = ¤t_cpu_data;
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unsigned int cpu = smp_processor_id();
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/*
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* Set a default elf platform, cpu probe may later
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* overwrite it with a more precise value
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*/
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set_elf_platform(cpu, "mips");
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c->processor_id = PRID_IMP_UNKNOWN;
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c->fpu_id = FPIR_IMP_NONE;
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c->cputype = CPU_UNKNOWN;
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c->writecombine = _CACHE_UNCACHED;
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c->fpu_csr31 = FPU_CSR_RN;
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c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008 |
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FPU_CSR_CONDX | FPU_CSR_FS;
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c->srsets = 1;
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c->processor_id = read_c0_prid();
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switch (c->processor_id & (PRID_COMP_MASK | PRID_IMP_MASK)) {
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case PRID_COMP_LEGACY | PRID_IMP_R2000:
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c->cputype = CPU_R2000;
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__cpu_name[cpu] = "R2000";
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c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
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MIPS_CPU_NOFPUEX;
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if (__cpu_has_fpu())
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c->options |= MIPS_CPU_FPU;
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c->tlbsize = 64;
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break;
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case PRID_COMP_LEGACY | PRID_IMP_R3000:
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if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
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if (cpu_has_confreg()) {
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c->cputype = CPU_R3081E;
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__cpu_name[cpu] = "R3081";
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} else {
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c->cputype = CPU_R3000A;
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__cpu_name[cpu] = "R3000A";
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}
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} else {
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c->cputype = CPU_R3000;
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__cpu_name[cpu] = "R3000";
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}
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c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
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MIPS_CPU_NOFPUEX;
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if (__cpu_has_fpu())
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c->options |= MIPS_CPU_FPU;
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c->tlbsize = 64;
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break;
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case PRID_COMP_LEGACY | PRID_IMP_TX39:
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c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
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if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
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c->cputype = CPU_TX3927;
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__cpu_name[cpu] = "TX3927";
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c->tlbsize = 64;
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} else {
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switch (c->processor_id & PRID_REV_MASK) {
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case PRID_REV_TX3912:
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c->cputype = CPU_TX3912;
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__cpu_name[cpu] = "TX3912";
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c->tlbsize = 32;
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break;
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case PRID_REV_TX3922:
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c->cputype = CPU_TX3922;
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__cpu_name[cpu] = "TX3922";
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c->tlbsize = 64;
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break;
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}
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}
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break;
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}
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BUG_ON(!__cpu_name[cpu]);
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BUG_ON(c->cputype == CPU_UNKNOWN);
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/*
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* Platform code can force the cpu type to optimize code
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* generation. In that case be sure the cpu type is correctly
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* manually setup otherwise it could trigger some nasty bugs.
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*/
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BUG_ON(current_cpu_type() != c->cputype);
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if (mips_fpu_disabled)
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c->options &= ~MIPS_CPU_FPU;
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if (c->options & MIPS_CPU_FPU)
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cpu_set_fpu_opts(c);
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else
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cpu_set_nofpu_opts(c);
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reserve_exception_space(0, 0x400);
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}
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void cpu_report(void)
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{
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struct cpuinfo_mips *c = ¤t_cpu_data;
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pr_info("CPU%d revision is: %08x (%s)\n",
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smp_processor_id(), c->processor_id, cpu_name_string());
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if (c->options & MIPS_CPU_FPU)
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pr_info("FPU revision is: %08x\n", c->fpu_id);
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}
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