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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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![Paul Cercueil](/assets/img/avatar_default.png)
Commit6654111c89
("MIPS: vmlinux.lds.S: align raw appended dtb to 8 bytes") changed the alignment from STRUCT_ALIGNMENT bytes to 8 bytes. The commit's message makes it sound like it was actually done on purpose, but this is not the case. The commit was written when raw appended dtb were not aligned at all. The STRUCT_ALIGN() was added a few days before, in commit7a05293af3
("MIPS: boot/compressed: Copy DTB to aligned address"). The true purpose of the commit was not to align specifically to 8 bytes, but to make sure that the generated vmlinux' size was properly padded to the alignment required for DTBs. While the switch to 8-byte alignment worked for vmlinux-appended dtb blobs, it broke vmlinuz-appended dtb blobs, as the decompress routine moves the blob to a STRUCT_ALIGNMENT aligned address. Fix this by changing the raw appended dtb blob alignment from 8 bytes back to STRUCT_ALIGNMENT bytes in vmlinux.lds.S. Fixes:6654111c89
("MIPS: vmlinux.lds.S: align raw appended dtb to 8 bytes") Cc: Bjørn Mork <bjorn@mork.no> Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
241 lines
4.9 KiB
ArmAsm
241 lines
4.9 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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#include <asm/asm-offsets.h>
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#include <asm/thread_info.h>
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#define PAGE_SIZE _PAGE_SIZE
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/*
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* Put .bss..swapper_pg_dir as the first thing in .bss. This will
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* ensure that it has .bss alignment (64K).
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*/
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#define BSS_FIRST_SECTIONS *(.bss..swapper_pg_dir)
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/* Cavium Octeon should not have a separate PT_NOTE Program Header. */
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#ifndef CONFIG_CAVIUM_OCTEON_SOC
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#define EMITS_PT_NOTE
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#endif
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#include <asm-generic/vmlinux.lds.h>
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#undef mips
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#define mips mips
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OUTPUT_ARCH(mips)
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ENTRY(kernel_entry)
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PHDRS {
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text PT_LOAD FLAGS(7); /* RWX */
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#ifndef CONFIG_CAVIUM_OCTEON_SOC
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note PT_NOTE FLAGS(4); /* R__ */
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#endif /* CAVIUM_OCTEON_SOC */
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}
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#ifdef CONFIG_32BIT
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#ifdef CONFIG_CPU_LITTLE_ENDIAN
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jiffies = jiffies_64;
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#else
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jiffies = jiffies_64 + 4;
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#endif
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#else
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jiffies = jiffies_64;
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#endif
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SECTIONS
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{
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#ifdef CONFIG_BOOT_ELF64
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/* Read-only sections, merged into text segment: */
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/* . = 0xc000000000000000; */
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/* This is the value for an Origin kernel, taken from an IRIX kernel. */
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/* . = 0xc00000000001c000; */
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/* Set the vaddr for the text segment to a value
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* >= 0xa800 0000 0001 9000 if no symmon is going to configured
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* >= 0xa800 0000 0030 0000 otherwise
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*/
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/* . = 0xa800000000300000; */
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. = 0xffffffff80300000;
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#endif
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. = LINKER_LOAD_ADDRESS;
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/* read-only */
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_text = .; /* Text and read-only data */
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.text : {
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TEXT_TEXT
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SCHED_TEXT
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CPUIDLE_TEXT
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LOCK_TEXT
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KPROBES_TEXT
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IRQENTRY_TEXT
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SOFTIRQENTRY_TEXT
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*(.fixup)
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*(.gnu.warning)
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. = ALIGN(16);
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*(.got) /* Global offset table */
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} :text = 0
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_etext = .; /* End of text section */
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EXCEPTION_TABLE(16)
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/* Exception table for data bus errors */
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__dbe_table : {
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__start___dbe_table = .;
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KEEP(*(__dbe_table))
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__stop___dbe_table = .;
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}
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_sdata = .; /* Start of data section */
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RO_DATA(4096)
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/* writeable */
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.data : { /* Data */
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. = . + DATAOFFSET; /* for CONFIG_MAPPED_KERNEL */
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INIT_TASK_DATA(THREAD_SIZE)
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NOSAVE_DATA
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PAGE_ALIGNED_DATA(PAGE_SIZE)
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CACHELINE_ALIGNED_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
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READ_MOSTLY_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
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DATA_DATA
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CONSTRUCTORS
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}
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BUG_TABLE
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_gp = . + 0x8000;
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.lit8 : {
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*(.lit8)
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}
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.lit4 : {
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*(.lit4)
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}
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/* We want the small data sections together, so single-instruction offsets
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can access them all, and initialized data all before uninitialized, so
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we can shorten the on-disk segment size. */
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.sdata : {
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*(.sdata)
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}
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_edata = .; /* End of data section */
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/* will be freed after init */
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. = ALIGN(PAGE_SIZE); /* Init code and data */
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__init_begin = .;
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INIT_TEXT_SECTION(PAGE_SIZE)
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INIT_DATA_SECTION(16)
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. = ALIGN(4);
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.mips.machines.init : AT(ADDR(.mips.machines.init) - LOAD_OFFSET) {
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__mips_machines_start = .;
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KEEP(*(.mips.machines.init))
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__mips_machines_end = .;
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}
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/* .exit.text is discarded at runtime, not link time, to deal with
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* references from .rodata
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*/
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.exit.text : {
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EXIT_TEXT
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}
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.exit.data : {
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EXIT_DATA
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}
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#ifdef CONFIG_SMP
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PERCPU_SECTION(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
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#endif
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.rel.dyn : ALIGN(8) {
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*(.rel)
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*(.rel*)
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}
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#ifdef CONFIG_MIPS_ELF_APPENDED_DTB
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STRUCT_ALIGN();
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.appended_dtb : AT(ADDR(.appended_dtb) - LOAD_OFFSET) {
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*(.appended_dtb)
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KEEP(*(.appended_dtb))
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}
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#endif
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#ifdef CONFIG_RELOCATABLE
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. = ALIGN(4);
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.data.reloc : {
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_relocation_start = .;
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/*
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* Space for relocation table
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* This needs to be filled so that the
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* relocs tool can overwrite the content.
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* An invalid value is left at the start of the
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* section to abort relocation if the table
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* has not been filled in.
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*/
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LONG(0xFFFFFFFF);
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FILL(0);
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. += CONFIG_RELOCATION_TABLE_SIZE - 4;
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_relocation_end = .;
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}
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#endif
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#ifdef CONFIG_MIPS_RAW_APPENDED_DTB
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.fill : {
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FILL(0);
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BYTE(0);
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STRUCT_ALIGN();
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}
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__appended_dtb = .;
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/* leave space for appended DTB */
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. += 0x100000;
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#endif
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/*
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* Align to 64K in attempt to eliminate holes before the
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* .bss..swapper_pg_dir section at the start of .bss. This
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* also satisfies PAGE_SIZE alignment as the largest page size
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* allowed is 64K.
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*/
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. = ALIGN(0x10000);
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__init_end = .;
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/* freed after init ends here */
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/*
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* Force .bss to 64K alignment so that .bss..swapper_pg_dir
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* gets that alignment. .sbss should be empty, so there will be
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* no holes after __init_end. */
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BSS_SECTION(0, 0x10000, 8)
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_end = . ;
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/* These mark the ABI of the kernel for debuggers. */
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.mdebug.abi32 : {
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KEEP(*(.mdebug.abi32))
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}
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.mdebug.abi64 : {
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KEEP(*(.mdebug.abi64))
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}
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/* This is the MIPS specific mdebug section. */
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.mdebug : {
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*(.mdebug)
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}
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STABS_DEBUG
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DWARF_DEBUG
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ELF_DETAILS
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/* These must appear regardless of . */
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.gptab.sdata : {
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*(.gptab.data)
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*(.gptab.sdata)
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}
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.gptab.sbss : {
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*(.gptab.bss)
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*(.gptab.sbss)
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}
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/* Sections to be discarded */
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DISCARDS
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/DISCARD/ : {
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/* ABI crap starts here */
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*(.MIPS.abiflags)
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*(.MIPS.options)
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*(.gnu.attributes)
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*(.options)
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*(.pdr)
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*(.reginfo)
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}
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}
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