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![Wan Ahmad Zainie](/assets/img/avatar_default.png)
Rename phy-intel-{combo,emmc}.c to phy-intel-lgm-{combo,emmc}.c to make drivers/phy/intel directory more generic for future use. Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com> Reviewed-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> Link: https://lore.kernel.org/r/20200913235522.4316-2-wan.ahmad.zainie.wan.mohamad@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
284 lines
7.6 KiB
C
284 lines
7.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Intel eMMC PHY driver
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* Copyright (C) 2019 Intel, Corp.
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*/
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#include <linux/bits.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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/* eMMC phy register definitions */
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#define EMMC_PHYCTRL0_REG 0xa8
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#define DR_TY_MASK GENMASK(30, 28)
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#define DR_TY_SHIFT(x) (((x) << 28) & DR_TY_MASK)
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#define OTAPDLYENA BIT(14)
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#define OTAPDLYSEL_MASK GENMASK(13, 10)
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#define OTAPDLYSEL_SHIFT(x) (((x) << 10) & OTAPDLYSEL_MASK)
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#define EMMC_PHYCTRL1_REG 0xac
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#define PDB_MASK BIT(0)
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#define PDB_SHIFT(x) (((x) << 0) & PDB_MASK)
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#define ENDLL_MASK BIT(7)
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#define ENDLL_SHIFT(x) (((x) << 7) & ENDLL_MASK)
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#define EMMC_PHYCTRL2_REG 0xb0
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#define FRQSEL_25M 0
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#define FRQSEL_50M 1
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#define FRQSEL_100M 2
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#define FRQSEL_150M 3
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#define FRQSEL_MASK GENMASK(24, 22)
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#define FRQSEL_SHIFT(x) (((x) << 22) & FRQSEL_MASK)
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#define EMMC_PHYSTAT_REG 0xbc
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#define CALDONE_MASK BIT(9)
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#define DLLRDY_MASK BIT(8)
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#define IS_CALDONE(x) ((x) & CALDONE_MASK)
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#define IS_DLLRDY(x) ((x) & DLLRDY_MASK)
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struct intel_emmc_phy {
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struct regmap *syscfg;
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struct clk *emmcclk;
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};
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static int intel_emmc_phy_power(struct phy *phy, bool on_off)
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{
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struct intel_emmc_phy *priv = phy_get_drvdata(phy);
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unsigned int caldone;
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unsigned int dllrdy;
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unsigned int freqsel;
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unsigned long rate;
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int ret, quot;
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/*
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* Keep phyctrl_pdb and phyctrl_endll low to allow
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* initialization of CALIO state M/C DFFs
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*/
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ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, PDB_MASK,
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PDB_SHIFT(0));
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if (ret) {
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dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret);
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return ret;
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}
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/* Already finish power_off above */
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if (!on_off)
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return 0;
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rate = clk_get_rate(priv->emmcclk);
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quot = DIV_ROUND_CLOSEST(rate, 50000000);
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if (quot > FRQSEL_150M)
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dev_warn(&phy->dev, "Unsupported rate: %lu\n", rate);
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freqsel = clamp_t(int, quot, FRQSEL_25M, FRQSEL_150M);
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/*
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* According to the user manual, calpad calibration
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* cycle takes more than 2us without the minimal recommended
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* value, so we may need a little margin here
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*/
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udelay(5);
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ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, PDB_MASK,
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PDB_SHIFT(1));
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if (ret) {
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dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret);
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return ret;
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}
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/*
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* According to the user manual, it asks driver to wait 5us for
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* calpad busy trimming. However it is documented that this value is
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* PVT(A.K.A process,voltage and temperature) relevant, so some
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* failure cases are found which indicates we should be more tolerant
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* to calpad busy trimming.
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*/
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ret = regmap_read_poll_timeout(priv->syscfg, EMMC_PHYSTAT_REG,
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caldone, IS_CALDONE(caldone),
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0, 50);
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if (ret) {
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dev_err(&phy->dev, "caldone failed, ret=%d\n", ret);
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return ret;
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}
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/* Set the frequency of the DLL operation */
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ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL2_REG, FRQSEL_MASK,
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FRQSEL_SHIFT(freqsel));
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if (ret) {
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dev_err(&phy->dev, "set the frequency of dll failed:%d\n", ret);
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return ret;
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}
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/* Turn on the DLL */
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ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, ENDLL_MASK,
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ENDLL_SHIFT(1));
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if (ret) {
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dev_err(&phy->dev, "turn on the dll failed: %d\n", ret);
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return ret;
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}
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/*
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* After enabling analog DLL circuits docs say that we need 10.2 us if
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* our source clock is at 50 MHz and that lock time scales linearly
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* with clock speed. If we are powering on the PHY and the card clock
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* is super slow (like 100 kHZ) this could take as long as 5.1 ms as
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* per the math: 10.2 us * (50000000 Hz / 100000 Hz) => 5.1 ms
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* Hopefully we won't be running at 100 kHz, but we should still make
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* sure we wait long enough.
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*
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* NOTE: There appear to be corner cases where the DLL seems to take
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* extra long to lock for reasons that aren't understood. In some
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* extreme cases we've seen it take up to over 10ms (!). We'll be
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* generous and give it 50ms.
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*/
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ret = regmap_read_poll_timeout(priv->syscfg,
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EMMC_PHYSTAT_REG,
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dllrdy, IS_DLLRDY(dllrdy),
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0, 50 * USEC_PER_MSEC);
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if (ret) {
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dev_err(&phy->dev, "dllrdy failed. ret=%d\n", ret);
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return ret;
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}
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return 0;
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}
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static int intel_emmc_phy_init(struct phy *phy)
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{
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struct intel_emmc_phy *priv = phy_get_drvdata(phy);
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/*
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* We purposely get the clock here and not in probe to avoid the
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* circular dependency problem. We expect:
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* - PHY driver to probe
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* - SDHCI driver to start probe
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* - SDHCI driver to register it's clock
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* - SDHCI driver to get the PHY
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* - SDHCI driver to init the PHY
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*
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* The clock is optional, so upon any error just return it like
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* any other error to user.
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*
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*/
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priv->emmcclk = clk_get_optional(&phy->dev, "emmcclk");
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if (IS_ERR(priv->emmcclk)) {
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dev_err(&phy->dev, "ERROR: getting emmcclk\n");
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return PTR_ERR(priv->emmcclk);
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}
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return 0;
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}
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static int intel_emmc_phy_exit(struct phy *phy)
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{
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struct intel_emmc_phy *priv = phy_get_drvdata(phy);
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clk_put(priv->emmcclk);
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return 0;
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}
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static int intel_emmc_phy_power_on(struct phy *phy)
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{
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struct intel_emmc_phy *priv = phy_get_drvdata(phy);
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int ret;
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/* Drive impedance: 50 Ohm */
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ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL0_REG, DR_TY_MASK,
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DR_TY_SHIFT(6));
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if (ret) {
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dev_err(&phy->dev, "ERROR set drive-impednce-50ohm: %d\n", ret);
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return ret;
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}
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/* Output tap delay: disable */
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ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL0_REG, OTAPDLYENA,
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0);
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if (ret) {
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dev_err(&phy->dev, "ERROR Set output tap delay : %d\n", ret);
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return ret;
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}
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/* Output tap delay */
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ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL0_REG,
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OTAPDLYSEL_MASK, OTAPDLYSEL_SHIFT(4));
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if (ret) {
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dev_err(&phy->dev, "ERROR: output tap dly select: %d\n", ret);
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return ret;
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}
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/* Power up eMMC phy analog blocks */
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return intel_emmc_phy_power(phy, true);
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}
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static int intel_emmc_phy_power_off(struct phy *phy)
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{
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/* Power down eMMC phy analog blocks */
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return intel_emmc_phy_power(phy, false);
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}
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static const struct phy_ops ops = {
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.init = intel_emmc_phy_init,
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.exit = intel_emmc_phy_exit,
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.power_on = intel_emmc_phy_power_on,
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.power_off = intel_emmc_phy_power_off,
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.owner = THIS_MODULE,
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};
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static int intel_emmc_phy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct intel_emmc_phy *priv;
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struct phy *generic_phy;
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struct phy_provider *phy_provider;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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/* Get eMMC phy (accessed via chiptop) regmap */
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priv->syscfg = syscon_regmap_lookup_by_phandle(np, "intel,syscon");
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if (IS_ERR(priv->syscfg)) {
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dev_err(dev, "failed to find syscon\n");
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return PTR_ERR(priv->syscfg);
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}
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generic_phy = devm_phy_create(dev, np, &ops);
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if (IS_ERR(generic_phy)) {
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dev_err(dev, "failed to create PHY\n");
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return PTR_ERR(generic_phy);
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}
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phy_set_drvdata(generic_phy, priv);
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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return PTR_ERR_OR_ZERO(phy_provider);
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}
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static const struct of_device_id intel_emmc_phy_dt_ids[] = {
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{ .compatible = "intel,lgm-emmc-phy" },
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{}
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};
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MODULE_DEVICE_TABLE(of, intel_emmc_phy_dt_ids);
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static struct platform_driver intel_emmc_driver = {
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.probe = intel_emmc_phy_probe,
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.driver = {
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.name = "intel-emmc-phy",
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.of_match_table = intel_emmc_phy_dt_ids,
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},
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};
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module_platform_driver(intel_emmc_driver);
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MODULE_AUTHOR("Peter Harliman Liem <peter.harliman.liem@intel.com>");
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MODULE_DESCRIPTION("Intel eMMC PHY driver");
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MODULE_LICENSE("GPL v2");
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