405 lines
10 KiB
C
405 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
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// http://www.samsung.com/
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//
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// Exynos - CPU PMU(Power Management Unit) support
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#include <linux/arm-smccc.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/regmap.h>
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#include <linux/soc/samsung/exynos-regs-pmu.h>
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#include <linux/soc/samsung/exynos-pmu.h>
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#include "exynos-pmu.h"
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#define PMUALIVE_MASK GENMASK(13, 0)
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#define TENSOR_SET_BITS (BIT(15) | BIT(14))
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#define TENSOR_CLR_BITS BIT(15)
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#define TENSOR_SMC_PMU_SEC_REG 0x82000504
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#define TENSOR_PMUREG_READ 0
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#define TENSOR_PMUREG_WRITE 1
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#define TENSOR_PMUREG_RMW 2
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struct exynos_pmu_context {
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struct device *dev;
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const struct exynos_pmu_data *pmu_data;
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struct regmap *pmureg;
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};
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void __iomem *pmu_base_addr;
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static struct exynos_pmu_context *pmu_context;
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/* forward declaration */
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static struct platform_driver exynos_pmu_driver;
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/*
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* Tensor SoCs are configured so that PMU_ALIVE registers can only be written
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* from EL3, but are still read accessible. As Linux needs to write some of
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* these registers, the following functions are provided and exposed via
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* regmap.
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*
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* Note: This SMC interface is known to be implemented on gs101 and derivative
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* SoCs.
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*/
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/* Write to a protected PMU register. */
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static int tensor_sec_reg_write(void *context, unsigned int reg,
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unsigned int val)
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{
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struct arm_smccc_res res;
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unsigned long pmu_base = (unsigned long)context;
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arm_smccc_smc(TENSOR_SMC_PMU_SEC_REG, pmu_base + reg,
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TENSOR_PMUREG_WRITE, val, 0, 0, 0, 0, &res);
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/* returns -EINVAL if access isn't allowed or 0 */
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if (res.a0)
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pr_warn("%s(): SMC failed: %d\n", __func__, (int)res.a0);
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return (int)res.a0;
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}
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/* Read/Modify/Write a protected PMU register. */
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static int tensor_sec_reg_rmw(void *context, unsigned int reg,
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unsigned int mask, unsigned int val)
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{
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struct arm_smccc_res res;
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unsigned long pmu_base = (unsigned long)context;
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arm_smccc_smc(TENSOR_SMC_PMU_SEC_REG, pmu_base + reg,
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TENSOR_PMUREG_RMW, mask, val, 0, 0, 0, &res);
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/* returns -EINVAL if access isn't allowed or 0 */
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if (res.a0)
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pr_warn("%s(): SMC failed: %d\n", __func__, (int)res.a0);
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return (int)res.a0;
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}
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/*
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* Read a protected PMU register. All PMU registers can be read by Linux.
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* Note: The SMC read register is not used, as only registers that can be
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* written are readable via SMC.
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*/
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static int tensor_sec_reg_read(void *context, unsigned int reg,
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unsigned int *val)
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{
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*val = pmu_raw_readl(reg);
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return 0;
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}
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/*
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* For SoCs that have set/clear bit hardware this function can be used when
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* the PMU register will be accessed by multiple masters.
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*
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* For example, to set bits 13:8 in PMU reg offset 0x3e80
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* tensor_set_bits_atomic(ctx, 0x3e80, 0x3f00, 0x3f00);
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*
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* Set bit 8, and clear bits 13:9 PMU reg offset 0x3e80
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* tensor_set_bits_atomic(0x3e80, 0x100, 0x3f00);
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*/
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static int tensor_set_bits_atomic(void *ctx, unsigned int offset, u32 val,
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u32 mask)
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{
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int ret;
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unsigned int i;
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for (i = 0; i < 32; i++) {
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if (!(mask & BIT(i)))
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continue;
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offset &= ~TENSOR_SET_BITS;
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if (val & BIT(i))
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offset |= TENSOR_SET_BITS;
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else
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offset |= TENSOR_CLR_BITS;
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ret = tensor_sec_reg_write(ctx, offset, i);
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if (ret)
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return ret;
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}
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return ret;
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}
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static int tensor_sec_update_bits(void *ctx, unsigned int reg,
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unsigned int mask, unsigned int val)
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{
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/*
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* Use atomic operations for PMU_ALIVE registers (offset 0~0x3FFF)
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* as the target registers can be accessed by multiple masters.
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*/
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if (reg > PMUALIVE_MASK)
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return tensor_sec_reg_rmw(ctx, reg, mask, val);
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return tensor_set_bits_atomic(ctx, reg, val, mask);
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}
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void pmu_raw_writel(u32 val, u32 offset)
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{
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writel_relaxed(val, pmu_base_addr + offset);
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}
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u32 pmu_raw_readl(u32 offset)
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{
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return readl_relaxed(pmu_base_addr + offset);
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}
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void exynos_sys_powerdown_conf(enum sys_powerdown mode)
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{
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unsigned int i;
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const struct exynos_pmu_data *pmu_data;
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if (!pmu_context || !pmu_context->pmu_data)
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return;
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pmu_data = pmu_context->pmu_data;
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if (pmu_data->powerdown_conf)
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pmu_data->powerdown_conf(mode);
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if (pmu_data->pmu_config) {
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for (i = 0; (pmu_data->pmu_config[i].offset != PMU_TABLE_END); i++)
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pmu_raw_writel(pmu_data->pmu_config[i].val[mode],
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pmu_data->pmu_config[i].offset);
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}
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if (pmu_data->powerdown_conf_extra)
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pmu_data->powerdown_conf_extra(mode);
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if (pmu_data->pmu_config_extra) {
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for (i = 0; pmu_data->pmu_config_extra[i].offset != PMU_TABLE_END; i++)
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pmu_raw_writel(pmu_data->pmu_config_extra[i].val[mode],
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pmu_data->pmu_config_extra[i].offset);
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}
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}
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/*
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* Split the data between ARM architectures because it is relatively big
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* and useless on other arch.
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*/
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#ifdef CONFIG_EXYNOS_PMU_ARM_DRIVERS
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#define exynos_pmu_data_arm_ptr(data) (&data)
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#else
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#define exynos_pmu_data_arm_ptr(data) NULL
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#endif
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static const struct regmap_config regmap_smccfg = {
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.name = "pmu_regs",
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.fast_io = true,
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.use_single_read = true,
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.use_single_write = true,
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.reg_read = tensor_sec_reg_read,
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.reg_write = tensor_sec_reg_write,
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.reg_update_bits = tensor_sec_update_bits,
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};
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static const struct regmap_config regmap_mmiocfg = {
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.name = "pmu_regs",
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.fast_io = true,
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.use_single_read = true,
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.use_single_write = true,
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};
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static const struct exynos_pmu_data gs101_pmu_data = {
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.pmu_secure = true
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};
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/*
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* PMU platform driver and devicetree bindings.
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*/
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static const struct of_device_id exynos_pmu_of_device_ids[] = {
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{
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.compatible = "google,gs101-pmu",
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.data = &gs101_pmu_data,
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}, {
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.compatible = "samsung,exynos3250-pmu",
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.data = exynos_pmu_data_arm_ptr(exynos3250_pmu_data),
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}, {
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.compatible = "samsung,exynos4210-pmu",
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.data = exynos_pmu_data_arm_ptr(exynos4210_pmu_data),
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}, {
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.compatible = "samsung,exynos4212-pmu",
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.data = exynos_pmu_data_arm_ptr(exynos4212_pmu_data),
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}, {
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.compatible = "samsung,exynos4412-pmu",
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.data = exynos_pmu_data_arm_ptr(exynos4412_pmu_data),
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}, {
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.compatible = "samsung,exynos5250-pmu",
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.data = exynos_pmu_data_arm_ptr(exynos5250_pmu_data),
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}, {
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.compatible = "samsung,exynos5410-pmu",
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}, {
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.compatible = "samsung,exynos5420-pmu",
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.data = exynos_pmu_data_arm_ptr(exynos5420_pmu_data),
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}, {
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.compatible = "samsung,exynos5433-pmu",
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}, {
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.compatible = "samsung,exynos7-pmu",
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}, {
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.compatible = "samsung,exynos850-pmu",
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},
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{ /*sentinel*/ },
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};
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static const struct mfd_cell exynos_pmu_devs[] = {
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{ .name = "exynos-clkout", },
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};
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/**
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* exynos_get_pmu_regmap() - Obtain pmureg regmap
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*
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* Find the pmureg regmap previously configured in probe() and return regmap
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* pointer.
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*
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* Return: A pointer to regmap if found or ERR_PTR error value.
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*/
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struct regmap *exynos_get_pmu_regmap(void)
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{
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struct device_node *np = of_find_matching_node(NULL,
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exynos_pmu_of_device_ids);
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if (np)
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return exynos_get_pmu_regmap_by_phandle(np, NULL);
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return ERR_PTR(-ENODEV);
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}
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EXPORT_SYMBOL_GPL(exynos_get_pmu_regmap);
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/**
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* exynos_get_pmu_regmap_by_phandle() - Obtain pmureg regmap via phandle
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* @np: Device node holding PMU phandle property
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* @propname: Name of property holding phandle value
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*
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* Find the pmureg regmap previously configured in probe() and return regmap
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* pointer.
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*
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* Return: A pointer to regmap if found or ERR_PTR error value.
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*/
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struct regmap *exynos_get_pmu_regmap_by_phandle(struct device_node *np,
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const char *propname)
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{
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struct exynos_pmu_context *ctx;
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struct device_node *pmu_np;
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struct device *dev;
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if (propname)
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pmu_np = of_parse_phandle(np, propname, 0);
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else
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pmu_np = np;
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if (!pmu_np)
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return ERR_PTR(-ENODEV);
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/*
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* Determine if exynos-pmu device has probed and therefore regmap
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* has been created and can be returned to the caller. Otherwise we
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* return -EPROBE_DEFER.
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*/
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dev = driver_find_device_by_of_node(&exynos_pmu_driver.driver,
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(void *)pmu_np);
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if (propname)
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of_node_put(pmu_np);
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if (!dev)
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return ERR_PTR(-EPROBE_DEFER);
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ctx = dev_get_drvdata(dev);
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return ctx->pmureg;
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}
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EXPORT_SYMBOL_GPL(exynos_get_pmu_regmap_by_phandle);
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static int exynos_pmu_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct regmap_config pmu_regmcfg;
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struct regmap *regmap;
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struct resource *res;
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int ret;
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pmu_base_addr = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(pmu_base_addr))
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return PTR_ERR(pmu_base_addr);
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pmu_context = devm_kzalloc(&pdev->dev,
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sizeof(struct exynos_pmu_context),
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GFP_KERNEL);
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if (!pmu_context)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -ENODEV;
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pmu_context->pmu_data = of_device_get_match_data(dev);
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/* For SoCs that secure PMU register writes use custom regmap */
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if (pmu_context->pmu_data && pmu_context->pmu_data->pmu_secure) {
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pmu_regmcfg = regmap_smccfg;
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pmu_regmcfg.max_register = resource_size(res) -
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pmu_regmcfg.reg_stride;
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/* Need physical address for SMC call */
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regmap = devm_regmap_init(dev, NULL,
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(void *)(uintptr_t)res->start,
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&pmu_regmcfg);
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} else {
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/* All other SoCs use a MMIO regmap */
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pmu_regmcfg = regmap_mmiocfg;
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pmu_regmcfg.max_register = resource_size(res) -
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pmu_regmcfg.reg_stride;
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regmap = devm_regmap_init_mmio(dev, pmu_base_addr,
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&pmu_regmcfg);
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}
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if (IS_ERR(regmap))
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return dev_err_probe(&pdev->dev, PTR_ERR(regmap),
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"regmap init failed\n");
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pmu_context->pmureg = regmap;
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pmu_context->dev = dev;
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if (pmu_context->pmu_data && pmu_context->pmu_data->pmu_init)
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pmu_context->pmu_data->pmu_init();
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platform_set_drvdata(pdev, pmu_context);
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ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, exynos_pmu_devs,
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ARRAY_SIZE(exynos_pmu_devs), NULL, 0, NULL);
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if (ret)
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return ret;
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if (devm_of_platform_populate(dev))
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dev_err(dev, "Error populating children, reboot and poweroff might not work properly\n");
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dev_dbg(dev, "Exynos PMU Driver probe done\n");
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return 0;
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}
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static struct platform_driver exynos_pmu_driver = {
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.driver = {
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.name = "exynos-pmu",
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.of_match_table = exynos_pmu_of_device_ids,
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},
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.probe = exynos_pmu_probe,
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};
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static int __init exynos_pmu_init(void)
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{
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return platform_driver_register(&exynos_pmu_driver);
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}
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postcore_initcall(exynos_pmu_init);
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