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21e6bff5e0
There is a bug in the TLB preload caused by the pid not being shifted to the correct location in tlbmisc register. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Tested-by: Guenter Roeck <linux@roeck-us.net> |
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cacheflush.c | ||
dma-mapping.c | ||
extable.c | ||
fault.c | ||
init.c | ||
ioremap.c | ||
Makefile | ||
mmu_context.c | ||
pgtable.c | ||
tlb.c | ||
uaccess.c |