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![Matt Redfearn](/assets/img/avatar_default.png)
Always accessing the compare register via the CM redirect region is (relatively) slow. If the timer being updated is the current CPUs then this can be shortcutted by writing to the CM VP local region. Signed-off-by: Matt Redfearn <matt.redfearn@mips.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
232 lines
5.4 KiB
C
232 lines
5.4 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
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*/
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/cpu.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/notifier.h>
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#include <linux/of_irq.h>
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#include <linux/percpu.h>
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#include <linux/smp.h>
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#include <linux/time.h>
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#include <asm/mips-cps.h>
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static DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device);
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static int gic_timer_irq;
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static unsigned int gic_frequency;
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static u64 notrace gic_read_count(void)
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{
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unsigned int hi, hi2, lo;
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if (mips_cm_is64)
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return read_gic_counter();
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do {
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hi = read_gic_counter_32h();
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lo = read_gic_counter_32l();
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hi2 = read_gic_counter_32h();
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} while (hi2 != hi);
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return (((u64) hi) << 32) + lo;
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}
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static int gic_next_event(unsigned long delta, struct clock_event_device *evt)
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{
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int cpu = cpumask_first(evt->cpumask);
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u64 cnt;
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int res;
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cnt = gic_read_count();
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cnt += (u64)delta;
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if (cpu == raw_smp_processor_id()) {
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write_gic_vl_compare(cnt);
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} else {
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write_gic_vl_other(mips_cm_vp_id(cpu));
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write_gic_vo_compare(cnt);
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}
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res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0;
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return res;
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}
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static irqreturn_t gic_compare_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *cd = dev_id;
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write_gic_vl_compare(read_gic_vl_compare());
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cd->event_handler(cd);
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return IRQ_HANDLED;
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}
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struct irqaction gic_compare_irqaction = {
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.handler = gic_compare_interrupt,
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.percpu_dev_id = &gic_clockevent_device,
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.flags = IRQF_PERCPU | IRQF_TIMER,
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.name = "timer",
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};
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static void gic_clockevent_cpu_init(unsigned int cpu,
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struct clock_event_device *cd)
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{
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cd->name = "MIPS GIC";
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cd->features = CLOCK_EVT_FEAT_ONESHOT |
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CLOCK_EVT_FEAT_C3STOP;
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cd->rating = 350;
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cd->irq = gic_timer_irq;
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cd->cpumask = cpumask_of(cpu);
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cd->set_next_event = gic_next_event;
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clockevents_config_and_register(cd, gic_frequency, 0x300, 0x7fffffff);
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enable_percpu_irq(gic_timer_irq, IRQ_TYPE_NONE);
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}
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static void gic_clockevent_cpu_exit(struct clock_event_device *cd)
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{
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disable_percpu_irq(gic_timer_irq);
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}
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static void gic_update_frequency(void *data)
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{
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unsigned long rate = (unsigned long)data;
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clockevents_update_freq(this_cpu_ptr(&gic_clockevent_device), rate);
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}
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static int gic_starting_cpu(unsigned int cpu)
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{
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gic_clockevent_cpu_init(cpu, this_cpu_ptr(&gic_clockevent_device));
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return 0;
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}
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static int gic_clk_notifier(struct notifier_block *nb, unsigned long action,
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void *data)
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{
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struct clk_notifier_data *cnd = data;
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if (action == POST_RATE_CHANGE)
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on_each_cpu(gic_update_frequency, (void *)cnd->new_rate, 1);
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return NOTIFY_OK;
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}
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static int gic_dying_cpu(unsigned int cpu)
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{
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gic_clockevent_cpu_exit(this_cpu_ptr(&gic_clockevent_device));
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return 0;
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}
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static struct notifier_block gic_clk_nb = {
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.notifier_call = gic_clk_notifier,
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};
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static int gic_clockevent_init(void)
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{
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int ret;
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if (!gic_frequency)
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return -ENXIO;
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ret = setup_percpu_irq(gic_timer_irq, &gic_compare_irqaction);
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if (ret < 0) {
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pr_err("GIC timer IRQ %d setup failed: %d\n",
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gic_timer_irq, ret);
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return ret;
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}
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cpuhp_setup_state(CPUHP_AP_MIPS_GIC_TIMER_STARTING,
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"clockevents/mips/gic/timer:starting",
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gic_starting_cpu, gic_dying_cpu);
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return 0;
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}
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static u64 gic_hpt_read(struct clocksource *cs)
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{
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return gic_read_count();
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}
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static struct clocksource gic_clocksource = {
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.name = "GIC",
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.read = gic_hpt_read,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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.archdata = { .vdso_clock_mode = VDSO_CLOCK_GIC },
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};
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static int __init __gic_clocksource_init(void)
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{
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unsigned int count_width;
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int ret;
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/* Set clocksource mask. */
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count_width = read_gic_config() & GIC_CONFIG_COUNTBITS;
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count_width >>= __fls(GIC_CONFIG_COUNTBITS);
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count_width *= 4;
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count_width += 32;
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gic_clocksource.mask = CLOCKSOURCE_MASK(count_width);
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/* Calculate a somewhat reasonable rating value. */
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gic_clocksource.rating = 200 + gic_frequency / 10000000;
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ret = clocksource_register_hz(&gic_clocksource, gic_frequency);
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if (ret < 0)
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pr_warn("GIC: Unable to register clocksource\n");
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return ret;
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}
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static int __init gic_clocksource_of_init(struct device_node *node)
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{
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struct clk *clk;
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int ret;
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if (!mips_gic_present() || !node->parent ||
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!of_device_is_compatible(node->parent, "mti,gic")) {
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pr_warn("No DT definition for the mips gic driver\n");
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return -ENXIO;
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}
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clk = of_clk_get(node, 0);
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if (!IS_ERR(clk)) {
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ret = clk_prepare_enable(clk);
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if (ret < 0) {
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pr_err("GIC failed to enable clock\n");
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clk_put(clk);
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return ret;
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}
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gic_frequency = clk_get_rate(clk);
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} else if (of_property_read_u32(node, "clock-frequency",
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&gic_frequency)) {
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pr_err("GIC frequency not specified.\n");
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return -EINVAL;;
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}
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gic_timer_irq = irq_of_parse_and_map(node, 0);
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if (!gic_timer_irq) {
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pr_err("GIC timer IRQ not specified.\n");
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return -EINVAL;;
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}
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ret = __gic_clocksource_init();
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if (ret)
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return ret;
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ret = gic_clockevent_init();
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if (!ret && !IS_ERR(clk)) {
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if (clk_notifier_register(clk, &gic_clk_nb) < 0)
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pr_warn("GIC: Unable to register clock notifier\n");
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}
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/* And finally start the counter */
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clear_gic_config(GIC_CONFIG_COUNTSTOP);
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return 0;
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}
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TIMER_OF_DECLARE(mips_gic_timer, "mti,gic-timer",
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gic_clocksource_of_init);
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