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![Daniel Lezcano](/assets/img/avatar_default.png)
The CLOCKSOURCE_OF_DECLARE macro is used widely for the timers to declare the clocksource at early stage. However, this macro is also used to initialize the clockevent if any, or the clockevent only. It was originally suggested to declare another macro to initialize a clockevent, so in order to separate the two entities even they belong to the same IP. This was not accepted because of the impact on the DT where splitting a clocksource/clockevent definition does not make sense as it is a Linux concept not a hardware description. On the other side, the clocksource has not interrupt declared while the clockevent has, so it is easy from the driver to know if the description is for a clockevent or a clocksource, IOW it could be implemented at the driver level. So instead of dealing with a named clocksource macro, let's use a more generic one: TIMER_OF_DECLARE. The patch has not functional changes. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
218 lines
5.6 KiB
C
218 lines
5.6 KiB
C
/*
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* Pistachio clocksource based on general-purpose timers
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*
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* Copyright (C) 2015 Imagination Technologies
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#include <linux/clk.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/sched_clock.h>
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#include <linux/time.h>
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/* Top level reg */
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#define CR_TIMER_CTRL_CFG 0x00
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#define TIMER_ME_GLOBAL BIT(0)
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#define CR_TIMER_REV 0x10
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/* Timer specific registers */
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#define TIMER_CFG 0x20
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#define TIMER_ME_LOCAL BIT(0)
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#define TIMER_RELOAD_VALUE 0x24
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#define TIMER_CURRENT_VALUE 0x28
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#define TIMER_CURRENT_OVERFLOW_VALUE 0x2C
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#define TIMER_IRQ_STATUS 0x30
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#define TIMER_IRQ_CLEAR 0x34
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#define TIMER_IRQ_MASK 0x38
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#define PERIP_TIMER_CONTROL 0x90
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/* Timer specific configuration Values */
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#define RELOAD_VALUE 0xffffffff
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struct pistachio_clocksource {
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void __iomem *base;
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raw_spinlock_t lock;
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struct clocksource cs;
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};
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static struct pistachio_clocksource pcs_gpt;
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#define to_pistachio_clocksource(cs) \
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container_of(cs, struct pistachio_clocksource, cs)
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static inline u32 gpt_readl(void __iomem *base, u32 offset, u32 gpt_id)
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{
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return readl(base + 0x20 * gpt_id + offset);
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}
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static inline void gpt_writel(void __iomem *base, u32 value, u32 offset,
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u32 gpt_id)
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{
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writel(value, base + 0x20 * gpt_id + offset);
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}
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static u64 notrace
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pistachio_clocksource_read_cycles(struct clocksource *cs)
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{
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struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs);
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u32 counter, overflw;
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unsigned long flags;
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/*
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* The counter value is only refreshed after the overflow value is read.
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* And they must be read in strict order, hence raw spin lock added.
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*/
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raw_spin_lock_irqsave(&pcs->lock, flags);
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overflw = gpt_readl(pcs->base, TIMER_CURRENT_OVERFLOW_VALUE, 0);
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counter = gpt_readl(pcs->base, TIMER_CURRENT_VALUE, 0);
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raw_spin_unlock_irqrestore(&pcs->lock, flags);
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return (u64)~counter;
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}
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static u64 notrace pistachio_read_sched_clock(void)
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{
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return pistachio_clocksource_read_cycles(&pcs_gpt.cs);
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}
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static void pistachio_clksrc_set_mode(struct clocksource *cs, int timeridx,
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int enable)
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{
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struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs);
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u32 val;
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val = gpt_readl(pcs->base, TIMER_CFG, timeridx);
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if (enable)
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val |= TIMER_ME_LOCAL;
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else
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val &= ~TIMER_ME_LOCAL;
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gpt_writel(pcs->base, val, TIMER_CFG, timeridx);
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}
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static void pistachio_clksrc_enable(struct clocksource *cs, int timeridx)
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{
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struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs);
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/* Disable GPT local before loading reload value */
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pistachio_clksrc_set_mode(cs, timeridx, false);
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gpt_writel(pcs->base, RELOAD_VALUE, TIMER_RELOAD_VALUE, timeridx);
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pistachio_clksrc_set_mode(cs, timeridx, true);
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}
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static void pistachio_clksrc_disable(struct clocksource *cs, int timeridx)
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{
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/* Disable GPT local */
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pistachio_clksrc_set_mode(cs, timeridx, false);
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}
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static int pistachio_clocksource_enable(struct clocksource *cs)
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{
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pistachio_clksrc_enable(cs, 0);
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return 0;
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}
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static void pistachio_clocksource_disable(struct clocksource *cs)
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{
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pistachio_clksrc_disable(cs, 0);
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}
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/* Desirable clock source for pistachio platform */
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static struct pistachio_clocksource pcs_gpt = {
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.cs = {
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.name = "gptimer",
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.rating = 300,
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.enable = pistachio_clocksource_enable,
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.disable = pistachio_clocksource_disable,
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.read = pistachio_clocksource_read_cycles,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS |
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CLOCK_SOURCE_SUSPEND_NONSTOP,
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},
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};
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static int __init pistachio_clksrc_of_init(struct device_node *node)
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{
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struct clk *sys_clk, *fast_clk;
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struct regmap *periph_regs;
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unsigned long rate;
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int ret;
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pcs_gpt.base = of_iomap(node, 0);
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if (!pcs_gpt.base) {
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pr_err("cannot iomap\n");
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return -ENXIO;
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}
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periph_regs = syscon_regmap_lookup_by_phandle(node, "img,cr-periph");
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if (IS_ERR(periph_regs)) {
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pr_err("cannot get peripheral regmap (%ld)\n",
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PTR_ERR(periph_regs));
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return PTR_ERR(periph_regs);
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}
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/* Switch to using the fast counter clock */
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ret = regmap_update_bits(periph_regs, PERIP_TIMER_CONTROL,
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0xf, 0x0);
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if (ret)
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return ret;
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sys_clk = of_clk_get_by_name(node, "sys");
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if (IS_ERR(sys_clk)) {
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pr_err("clock get failed (%ld)\n", PTR_ERR(sys_clk));
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return PTR_ERR(sys_clk);
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}
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fast_clk = of_clk_get_by_name(node, "fast");
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if (IS_ERR(fast_clk)) {
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pr_err("clock get failed (%lu)\n", PTR_ERR(fast_clk));
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return PTR_ERR(fast_clk);
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}
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ret = clk_prepare_enable(sys_clk);
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if (ret < 0) {
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pr_err("failed to enable clock (%d)\n", ret);
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return ret;
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}
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ret = clk_prepare_enable(fast_clk);
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if (ret < 0) {
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pr_err("failed to enable clock (%d)\n", ret);
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clk_disable_unprepare(sys_clk);
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return ret;
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}
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rate = clk_get_rate(fast_clk);
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/* Disable irq's for clocksource usage */
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gpt_writel(pcs_gpt.base, 0, TIMER_IRQ_MASK, 0);
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gpt_writel(pcs_gpt.base, 0, TIMER_IRQ_MASK, 1);
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gpt_writel(pcs_gpt.base, 0, TIMER_IRQ_MASK, 2);
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gpt_writel(pcs_gpt.base, 0, TIMER_IRQ_MASK, 3);
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/* Enable timer block */
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writel(TIMER_ME_GLOBAL, pcs_gpt.base);
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raw_spin_lock_init(&pcs_gpt.lock);
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sched_clock_register(pistachio_read_sched_clock, 32, rate);
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return clocksource_register_hz(&pcs_gpt.cs, rate);
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}
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TIMER_OF_DECLARE(pistachio_gptimer, "img,pistachio-gptimer",
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pistachio_clksrc_of_init);
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