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![Camuso, Tony](/assets/img/avatar_default.png)
Increase number of supported channels from 8 to 24. Make the number of channels configurable via module parameter max_ccb. Signed-off-by: Mark Rusk <mark.rusk@hp.com> Signed-off-by: Tony Camuso <tony.camuso@hp.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
214 lines
5.7 KiB
C
214 lines
5.7 KiB
C
/*
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* linux/drivers/char/hpilo.h
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*
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* Copyright (C) 2008 Hewlett-Packard Development Company, L.P.
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* David Altobelli <david.altobelli@hp.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __HPILO_H
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#define __HPILO_H
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#define ILO_NAME "hpilo"
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/* max number of open channel control blocks per device, hw limited to 32 */
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#define MAX_CCB 24
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/* min number of open channel control blocks per device, hw limited to 32 */
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#define MIN_CCB 8
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/* max number of supported devices */
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#define MAX_ILO_DEV 1
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/* max number of files */
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#define MAX_OPEN (MAX_CCB * MAX_ILO_DEV)
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/* total wait time in usec */
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#define MAX_WAIT_TIME 10000
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/* per spin wait time in usec */
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#define WAIT_TIME 10
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/* spin counter for open/close delay */
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#define MAX_WAIT (MAX_WAIT_TIME / WAIT_TIME)
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/*
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* Per device, used to track global memory allocations.
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*/
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struct ilo_hwinfo {
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/* mmio registers on device */
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char __iomem *mmio_vaddr;
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/* doorbell registers on device */
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char __iomem *db_vaddr;
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/* shared memory on device used for channel control blocks */
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char __iomem *ram_vaddr;
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/* files corresponding to this device */
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struct ccb_data *ccb_alloc[MAX_CCB];
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struct pci_dev *ilo_dev;
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/*
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* open_lock serializes ccb_cnt during open and close
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* [ irq disabled ]
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* -> alloc_lock used when adding/removing/searching ccb_alloc,
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* which represents all ccbs open on the device
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* --> fifo_lock controls access to fifo queues shared with hw
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*
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* Locks must be taken in this order, but open_lock and alloc_lock
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* are optional, they do not need to be held in order to take a
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* lower level lock.
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*/
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spinlock_t open_lock;
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spinlock_t alloc_lock;
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spinlock_t fifo_lock;
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struct cdev cdev;
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};
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/* offset from mmio_vaddr for enabling doorbell interrupts */
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#define DB_IRQ 0xB2
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/* offset from mmio_vaddr for outbound communications */
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#define DB_OUT 0xD4
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/* DB_OUT reset bit */
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#define DB_RESET 26
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/*
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* Channel control block. Used to manage hardware queues.
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* The format must match hw's version. The hw ccb is 128 bytes,
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* but the context area shouldn't be touched by the driver.
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*/
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#define ILOSW_CCB_SZ 64
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#define ILOHW_CCB_SZ 128
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struct ccb {
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union {
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char *send_fifobar;
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u64 send_fifobar_pa;
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} ccb_u1;
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union {
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char *send_desc;
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u64 send_desc_pa;
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} ccb_u2;
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u64 send_ctrl;
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union {
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char *recv_fifobar;
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u64 recv_fifobar_pa;
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} ccb_u3;
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union {
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char *recv_desc;
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u64 recv_desc_pa;
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} ccb_u4;
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u64 recv_ctrl;
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union {
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char __iomem *db_base;
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u64 padding5;
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} ccb_u5;
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u64 channel;
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/* unused context area (64 bytes) */
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};
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/* ccb queue parameters */
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#define SENDQ 1
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#define RECVQ 2
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#define NR_QENTRY 4
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#define L2_QENTRY_SZ 12
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/* ccb ctrl bitfields */
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#define CTRL_BITPOS_L2SZ 0
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#define CTRL_BITPOS_FIFOINDEXMASK 4
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#define CTRL_BITPOS_DESCLIMIT 18
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#define CTRL_BITPOS_A 30
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#define CTRL_BITPOS_G 31
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/* ccb doorbell macros */
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#define L2_DB_SIZE 14
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#define ONE_DB_SIZE (1 << L2_DB_SIZE)
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/*
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* Per fd structure used to track the ccb allocated to that dev file.
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*/
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struct ccb_data {
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/* software version of ccb, using virtual addrs */
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struct ccb driver_ccb;
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/* hardware version of ccb, using physical addrs */
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struct ccb ilo_ccb;
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/* hardware ccb is written to this shared mapped device memory */
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struct ccb __iomem *mapped_ccb;
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/* dma'able memory used for send/recv queues */
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void *dma_va;
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dma_addr_t dma_pa;
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size_t dma_size;
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/* pointer to hardware device info */
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struct ilo_hwinfo *ilo_hw;
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/* queue for this ccb to wait for recv data */
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wait_queue_head_t ccb_waitq;
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/* usage count, to allow for shared ccb's */
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int ccb_cnt;
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/* open wanted exclusive access to this ccb */
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int ccb_excl;
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};
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/*
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* FIFO queue structure, shared with hw.
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*/
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#define ILO_START_ALIGN 4096
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#define ILO_CACHE_SZ 128
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struct fifo {
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u64 nrents; /* user requested number of fifo entries */
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u64 imask; /* mask to extract valid fifo index */
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u64 merge; /* O/C bits to merge in during enqueue operation */
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u64 reset; /* set to non-zero when the target device resets */
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u8 pad_0[ILO_CACHE_SZ - (sizeof(u64) * 4)];
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u64 head;
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u8 pad_1[ILO_CACHE_SZ - (sizeof(u64))];
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u64 tail;
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u8 pad_2[ILO_CACHE_SZ - (sizeof(u64))];
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u64 fifobar[1];
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};
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/* convert between struct fifo, and the fifobar, which is saved in the ccb */
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#define FIFOHANDLESIZE (sizeof(struct fifo) - sizeof(u64))
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#define FIFOBARTOHANDLE(_fifo) \
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((struct fifo *)(((char *)(_fifo)) - FIFOHANDLESIZE))
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/* the number of qwords to consume from the entry descriptor */
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#define ENTRY_BITPOS_QWORDS 0
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/* descriptor index number (within a specified queue) */
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#define ENTRY_BITPOS_DESCRIPTOR 10
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/* state bit, fifo entry consumed by consumer */
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#define ENTRY_BITPOS_C 22
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/* state bit, fifo entry is occupied */
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#define ENTRY_BITPOS_O 23
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#define ENTRY_BITS_QWORDS 10
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#define ENTRY_BITS_DESCRIPTOR 12
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#define ENTRY_BITS_C 1
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#define ENTRY_BITS_O 1
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#define ENTRY_BITS_TOTAL \
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(ENTRY_BITS_C + ENTRY_BITS_O + \
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ENTRY_BITS_QWORDS + ENTRY_BITS_DESCRIPTOR)
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/* extract various entry fields */
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#define ENTRY_MASK ((1 << ENTRY_BITS_TOTAL) - 1)
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#define ENTRY_MASK_C (((1 << ENTRY_BITS_C) - 1) << ENTRY_BITPOS_C)
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#define ENTRY_MASK_O (((1 << ENTRY_BITS_O) - 1) << ENTRY_BITPOS_O)
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#define ENTRY_MASK_QWORDS \
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(((1 << ENTRY_BITS_QWORDS) - 1) << ENTRY_BITPOS_QWORDS)
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#define ENTRY_MASK_DESCRIPTOR \
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(((1 << ENTRY_BITS_DESCRIPTOR) - 1) << ENTRY_BITPOS_DESCRIPTOR)
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#define ENTRY_MASK_NOSTATE (ENTRY_MASK >> (ENTRY_BITS_C + ENTRY_BITS_O))
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#endif /* __HPILO_H */
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