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6b6c32fc96
Modify interrupt handling such that interrupts can be handled by GPMC client drivers using standard interrupt APIs rather than requiring the drivers to have knowledge about GPMC interrupt handling. Currently only NAND related interrupts has been considered (which is the case even without this change) as the only user of GPMC interrupt is NAND. Signed-off-by: Afzal Mohammed <afzal@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
190 lines
7.2 KiB
C
190 lines
7.2 KiB
C
/*
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* General-Purpose Memory Controller for OMAP2
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*
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* Copyright (C) 2005-2006 Nokia Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __OMAP2_GPMC_H
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#define __OMAP2_GPMC_H
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/* Maximum Number of Chip Selects */
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#define GPMC_CS_NUM 8
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#define GPMC_CS_CONFIG1 0x00
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#define GPMC_CS_CONFIG2 0x04
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#define GPMC_CS_CONFIG3 0x08
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#define GPMC_CS_CONFIG4 0x0c
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#define GPMC_CS_CONFIG5 0x10
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#define GPMC_CS_CONFIG6 0x14
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#define GPMC_CS_CONFIG7 0x18
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#define GPMC_CS_NAND_COMMAND 0x1c
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#define GPMC_CS_NAND_ADDRESS 0x20
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#define GPMC_CS_NAND_DATA 0x24
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/* Control Commands */
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#define GPMC_CONFIG_RDY_BSY 0x00000001
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#define GPMC_CONFIG_DEV_SIZE 0x00000002
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#define GPMC_CONFIG_DEV_TYPE 0x00000003
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#define GPMC_SET_IRQ_STATUS 0x00000004
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#define GPMC_CONFIG_WP 0x00000005
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#define GPMC_GET_IRQ_STATUS 0x00000006
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#define GPMC_PREFETCH_FIFO_CNT 0x00000007 /* bytes available in FIFO for r/w */
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#define GPMC_PREFETCH_COUNT 0x00000008 /* remaining bytes to be read/write*/
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#define GPMC_STATUS_BUFFER 0x00000009 /* 1: buffer is available to write */
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#define GPMC_NAND_COMMAND 0x0000000a
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#define GPMC_NAND_ADDRESS 0x0000000b
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#define GPMC_NAND_DATA 0x0000000c
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#define GPMC_ENABLE_IRQ 0x0000000d
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/* ECC commands */
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#define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
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#define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
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#define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
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#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
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#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
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#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
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#define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
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#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
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#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
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#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
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#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
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#define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
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#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
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#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
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#define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
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#define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
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#define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
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#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
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#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
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#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
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#define GPMC_CONFIG1_MUXADDDATA (1 << 9)
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#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
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#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
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#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
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#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
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#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
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#define GPMC_CONFIG7_CSVALID (1 << 6)
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#define GPMC_DEVICETYPE_NOR 0
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#define GPMC_DEVICETYPE_NAND 2
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#define GPMC_CONFIG_WRITEPROTECT 0x00000010
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#define GPMC_STATUS_BUFF_EMPTY 0x00000001
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#define WR_RD_PIN_MONITORING 0x00600000
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#define GPMC_PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F)
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#define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
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#define GPMC_IRQ_FIFOEVENTENABLE 0x01
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#define GPMC_IRQ_COUNT_EVENT 0x02
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#define PREFETCH_FIFOTHRESHOLD_MAX 0x40
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#define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
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enum omap_ecc {
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/* 1-bit ecc: stored at end of spare area */
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OMAP_ECC_HAMMING_CODE_DEFAULT = 0, /* Default, s/w method */
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OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */
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/* 1-bit ecc: stored at beginning of spare area as romcode */
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OMAP_ECC_HAMMING_CODE_HW_ROMCODE, /* gpmc method & romcode layout */
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OMAP_ECC_BCH4_CODE_HW, /* 4-bit BCH ecc code */
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OMAP_ECC_BCH8_CODE_HW, /* 8-bit BCH ecc code */
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};
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/*
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* Note that all values in this struct are in nanoseconds except sync_clk
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* (which is in picoseconds), while the register values are in gpmc_fck cycles.
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*/
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struct gpmc_timings {
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/* Minimum clock period for synchronous mode (in picoseconds) */
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u32 sync_clk;
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/* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
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u16 cs_on; /* Assertion time */
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u16 cs_rd_off; /* Read deassertion time */
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u16 cs_wr_off; /* Write deassertion time */
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/* ADV signal timings corresponding to GPMC_CONFIG3 */
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u16 adv_on; /* Assertion time */
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u16 adv_rd_off; /* Read deassertion time */
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u16 adv_wr_off; /* Write deassertion time */
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/* WE signals timings corresponding to GPMC_CONFIG4 */
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u16 we_on; /* WE assertion time */
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u16 we_off; /* WE deassertion time */
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/* OE signals timings corresponding to GPMC_CONFIG4 */
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u16 oe_on; /* OE assertion time */
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u16 oe_off; /* OE deassertion time */
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/* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
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u16 page_burst_access; /* Multiple access word delay */
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u16 access; /* Start-cycle to first data valid delay */
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u16 rd_cycle; /* Total read cycle time */
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u16 wr_cycle; /* Total write cycle time */
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/* The following are only on OMAP3430 */
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u16 wr_access; /* WRACCESSTIME */
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u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */
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};
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struct gpmc_nand_regs {
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void __iomem *gpmc_status;
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void __iomem *gpmc_nand_command;
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void __iomem *gpmc_nand_address;
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void __iomem *gpmc_nand_data;
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void __iomem *gpmc_prefetch_config1;
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void __iomem *gpmc_prefetch_config2;
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void __iomem *gpmc_prefetch_control;
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void __iomem *gpmc_prefetch_status;
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void __iomem *gpmc_ecc_config;
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void __iomem *gpmc_ecc_control;
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void __iomem *gpmc_ecc_size_config;
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void __iomem *gpmc_ecc1_result;
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void __iomem *gpmc_bch_result0;
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};
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extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
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extern int gpmc_get_client_irq(unsigned irq_config);
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extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
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extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps);
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extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
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extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
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extern unsigned long gpmc_get_fclk_period(void);
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extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
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extern u32 gpmc_cs_read_reg(int cs, int idx);
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extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk);
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extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
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extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
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extern void gpmc_cs_free(int cs);
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extern int gpmc_cs_set_reserved(int cs, int reserved);
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extern int gpmc_cs_reserved(int cs);
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extern int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
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unsigned int u32_count, int is_write);
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extern int gpmc_prefetch_reset(int cs);
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extern void omap3_gpmc_save_context(void);
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extern void omap3_gpmc_restore_context(void);
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extern int gpmc_read_status(int cmd);
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extern int gpmc_cs_configure(int cs, int cmd, int wval);
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extern int gpmc_nand_read(int cs, int cmd);
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extern int gpmc_nand_write(int cs, int cmd, int wval);
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int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size);
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int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code);
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#ifdef CONFIG_ARCH_OMAP3
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int gpmc_init_hwecc_bch(int cs, int nsectors, int nerrors);
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int gpmc_enable_hwecc_bch(int cs, int mode, int dev_width, int nsectors,
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int nerrors);
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int gpmc_calculate_ecc_bch4(int cs, const u_char *dat, u_char *ecc);
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int gpmc_calculate_ecc_bch8(int cs, const u_char *dat, u_char *ecc);
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#endif /* CONFIG_ARCH_OMAP3 */
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#endif
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