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b5f06f64e2
The goal of this is to allow tasks that want to protect sensitive
information, against e.g. the recently found snoop assisted data sampling
vulnerabilites, to flush their L1D on being switched out. This protects
their data from being snooped or leaked via side channels after the task
has context switched out.
This could also be used to wipe L1D when an untrusted task is switched in,
but that's not a really well defined scenario while the opt-in variant is
clearly defined.
The mechanism is default disabled and can be enabled on the kernel command
line.
Prepare for the actual prctl based opt-in:
1) Provide the necessary setup functionality similar to the other
mitigations and enable the static branch when the command line option
is set and the CPU provides support for hardware assisted L1D
flushing. Software based L1D flush is not supported because it's CPU
model specific and not really well defined.
This does not come with a sysfs file like the other mitigations
because it is not bound to any specific vulnerability.
Support has to be queried via the prctl(2) interface.
2) Add TIF_SPEC_L1D_FLUSH next to L1D_SPEC_IB so the two bits can be
mangled into the mm pointer in one go which allows to reuse the
existing mechanism in switch_mm() for the conditional IBPB speculation
barrier efficiently.
3) Add the L1D flush specific functionality which flushes L1D when the
outgoing task opted in.
Also check whether the incoming task has requested L1D flush and if so
validate that it is not accidentaly running on an SMT sibling as this
makes the whole excercise moot because SMT siblings share L1D which
opens tons of other attack vectors. If that happens schedule task work
which signals the incoming task on return to user/guest with SIGBUS as
this is part of the paranoid L1D flush contract.
Suggested-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Balbir Singh <sblbir@amazon.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20210108121056.21940-1-sblbir@amazon.com
365 lines
9.8 KiB
C
365 lines
9.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_NOSPEC_BRANCH_H_
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#define _ASM_X86_NOSPEC_BRANCH_H_
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#include <linux/static_key.h>
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#include <linux/objtool.h>
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#include <asm/alternative.h>
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#include <asm/cpufeatures.h>
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#include <asm/msr-index.h>
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#include <asm/unwind_hints.h>
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/*
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* Fill the CPU return stack buffer.
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*
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* Each entry in the RSB, if used for a speculative 'ret', contains an
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* infinite 'pause; lfence; jmp' loop to capture speculative execution.
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*
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* This is required in various cases for retpoline and IBRS-based
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* mitigations for the Spectre variant 2 vulnerability. Sometimes to
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* eliminate potentially bogus entries from the RSB, and sometimes
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* purely to ensure that it doesn't get empty, which on some CPUs would
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* allow predictions from other (unwanted!) sources to be used.
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*
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* We define a CPP macro such that it can be used from both .S files and
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* inline assembly. It's possible to do a .macro and then include that
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* from C via asm(".include <asm/nospec-branch.h>") but let's not go there.
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*/
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#define RSB_CLEAR_LOOPS 32 /* To forcibly overwrite all entries */
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/*
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* Google experimented with loop-unrolling and this turned out to be
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* the optimal version - two calls, each with their own speculation
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* trap should their return address end up getting used, in a loop.
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*/
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#define __FILL_RETURN_BUFFER(reg, nr, sp) \
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mov $(nr/2), reg; \
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771: \
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ANNOTATE_INTRA_FUNCTION_CALL; \
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call 772f; \
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773: /* speculation trap */ \
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UNWIND_HINT_EMPTY; \
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pause; \
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lfence; \
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jmp 773b; \
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772: \
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ANNOTATE_INTRA_FUNCTION_CALL; \
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call 774f; \
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775: /* speculation trap */ \
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UNWIND_HINT_EMPTY; \
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pause; \
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lfence; \
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jmp 775b; \
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774: \
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add $(BITS_PER_LONG/8) * 2, sp; \
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dec reg; \
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jnz 771b;
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#ifdef __ASSEMBLY__
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/*
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* This should be used immediately before an indirect jump/call. It tells
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* objtool the subsequent indirect jump/call is vouched safe for retpoline
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* builds.
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*/
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.macro ANNOTATE_RETPOLINE_SAFE
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.Lannotate_\@:
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.pushsection .discard.retpoline_safe
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_ASM_PTR .Lannotate_\@
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.popsection
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.endm
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/*
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* JMP_NOSPEC and CALL_NOSPEC macros can be used instead of a simple
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* indirect jmp/call which may be susceptible to the Spectre variant 2
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* attack.
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*/
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.macro JMP_NOSPEC reg:req
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#ifdef CONFIG_RETPOLINE
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ALTERNATIVE_2 __stringify(ANNOTATE_RETPOLINE_SAFE; jmp *%\reg), \
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__stringify(jmp __x86_indirect_thunk_\reg), X86_FEATURE_RETPOLINE, \
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__stringify(lfence; ANNOTATE_RETPOLINE_SAFE; jmp *%\reg), X86_FEATURE_RETPOLINE_AMD
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#else
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jmp *%\reg
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#endif
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.endm
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.macro CALL_NOSPEC reg:req
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#ifdef CONFIG_RETPOLINE
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ALTERNATIVE_2 __stringify(ANNOTATE_RETPOLINE_SAFE; call *%\reg), \
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__stringify(call __x86_indirect_thunk_\reg), X86_FEATURE_RETPOLINE, \
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__stringify(lfence; ANNOTATE_RETPOLINE_SAFE; call *%\reg), X86_FEATURE_RETPOLINE_AMD
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#else
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call *%\reg
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#endif
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.endm
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/*
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* A simpler FILL_RETURN_BUFFER macro. Don't make people use the CPP
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* monstrosity above, manually.
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*/
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.macro FILL_RETURN_BUFFER reg:req nr:req ftr:req
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#ifdef CONFIG_RETPOLINE
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ALTERNATIVE "jmp .Lskip_rsb_\@", "", \ftr
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__FILL_RETURN_BUFFER(\reg,\nr,%_ASM_SP)
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.Lskip_rsb_\@:
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#endif
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.endm
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#else /* __ASSEMBLY__ */
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#define ANNOTATE_RETPOLINE_SAFE \
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"999:\n\t" \
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".pushsection .discard.retpoline_safe\n\t" \
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_ASM_PTR " 999b\n\t" \
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".popsection\n\t"
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#ifdef CONFIG_RETPOLINE
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#ifdef CONFIG_X86_64
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/*
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* Inline asm uses the %V modifier which is only in newer GCC
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* which is ensured when CONFIG_RETPOLINE is defined.
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*/
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# define CALL_NOSPEC \
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ALTERNATIVE_2( \
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ANNOTATE_RETPOLINE_SAFE \
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"call *%[thunk_target]\n", \
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"call __x86_indirect_thunk_%V[thunk_target]\n", \
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X86_FEATURE_RETPOLINE, \
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"lfence;\n" \
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ANNOTATE_RETPOLINE_SAFE \
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"call *%[thunk_target]\n", \
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X86_FEATURE_RETPOLINE_AMD)
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# define THUNK_TARGET(addr) [thunk_target] "r" (addr)
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#else /* CONFIG_X86_32 */
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/*
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* For i386 we use the original ret-equivalent retpoline, because
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* otherwise we'll run out of registers. We don't care about CET
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* here, anyway.
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*/
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# define CALL_NOSPEC \
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ALTERNATIVE_2( \
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ANNOTATE_RETPOLINE_SAFE \
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"call *%[thunk_target]\n", \
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" jmp 904f;\n" \
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" .align 16\n" \
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"901: call 903f;\n" \
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"902: pause;\n" \
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" lfence;\n" \
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" jmp 902b;\n" \
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" .align 16\n" \
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"903: lea 4(%%esp), %%esp;\n" \
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" pushl %[thunk_target];\n" \
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" ret;\n" \
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" .align 16\n" \
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"904: call 901b;\n", \
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X86_FEATURE_RETPOLINE, \
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"lfence;\n" \
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ANNOTATE_RETPOLINE_SAFE \
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"call *%[thunk_target]\n", \
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X86_FEATURE_RETPOLINE_AMD)
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# define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
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#endif
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#else /* No retpoline for C / inline asm */
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# define CALL_NOSPEC "call *%[thunk_target]\n"
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# define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
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#endif
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/* The Spectre V2 mitigation variants */
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enum spectre_v2_mitigation {
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SPECTRE_V2_NONE,
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SPECTRE_V2_RETPOLINE_GENERIC,
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SPECTRE_V2_RETPOLINE_AMD,
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SPECTRE_V2_IBRS_ENHANCED,
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};
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/* The indirect branch speculation control variants */
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enum spectre_v2_user_mitigation {
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SPECTRE_V2_USER_NONE,
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SPECTRE_V2_USER_STRICT,
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SPECTRE_V2_USER_STRICT_PREFERRED,
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SPECTRE_V2_USER_PRCTL,
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SPECTRE_V2_USER_SECCOMP,
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};
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/* The Speculative Store Bypass disable variants */
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enum ssb_mitigation {
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SPEC_STORE_BYPASS_NONE,
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SPEC_STORE_BYPASS_DISABLE,
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SPEC_STORE_BYPASS_PRCTL,
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SPEC_STORE_BYPASS_SECCOMP,
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};
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extern char __indirect_thunk_start[];
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extern char __indirect_thunk_end[];
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static __always_inline
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void alternative_msr_write(unsigned int msr, u64 val, unsigned int feature)
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{
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asm volatile(ALTERNATIVE("", "wrmsr", %c[feature])
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: : "c" (msr),
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"a" ((u32)val),
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"d" ((u32)(val >> 32)),
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[feature] "i" (feature)
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: "memory");
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}
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static inline void indirect_branch_prediction_barrier(void)
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{
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u64 val = PRED_CMD_IBPB;
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alternative_msr_write(MSR_IA32_PRED_CMD, val, X86_FEATURE_USE_IBPB);
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}
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/* The Intel SPEC CTRL MSR base value cache */
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extern u64 x86_spec_ctrl_base;
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/*
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* With retpoline, we must use IBRS to restrict branch prediction
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* before calling into firmware.
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*
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* (Implemented as CPP macros due to header hell.)
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*/
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#define firmware_restrict_branch_speculation_start() \
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do { \
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u64 val = x86_spec_ctrl_base | SPEC_CTRL_IBRS; \
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\
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preempt_disable(); \
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alternative_msr_write(MSR_IA32_SPEC_CTRL, val, \
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X86_FEATURE_USE_IBRS_FW); \
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} while (0)
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#define firmware_restrict_branch_speculation_end() \
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do { \
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u64 val = x86_spec_ctrl_base; \
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\
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alternative_msr_write(MSR_IA32_SPEC_CTRL, val, \
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X86_FEATURE_USE_IBRS_FW); \
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preempt_enable(); \
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} while (0)
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DECLARE_STATIC_KEY_FALSE(switch_to_cond_stibp);
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DECLARE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
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DECLARE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
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DECLARE_STATIC_KEY_FALSE(mds_user_clear);
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DECLARE_STATIC_KEY_FALSE(mds_idle_clear);
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DECLARE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush);
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#include <asm/segment.h>
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/**
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* mds_clear_cpu_buffers - Mitigation for MDS and TAA vulnerability
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*
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* This uses the otherwise unused and obsolete VERW instruction in
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* combination with microcode which triggers a CPU buffer flush when the
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* instruction is executed.
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*/
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static __always_inline void mds_clear_cpu_buffers(void)
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{
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static const u16 ds = __KERNEL_DS;
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/*
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* Has to be the memory-operand variant because only that
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* guarantees the CPU buffer flush functionality according to
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* documentation. The register-operand variant does not.
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* Works with any segment selector, but a valid writable
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* data segment is the fastest variant.
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*
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* "cc" clobber is required because VERW modifies ZF.
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*/
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asm volatile("verw %[ds]" : : [ds] "m" (ds) : "cc");
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}
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/**
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* mds_user_clear_cpu_buffers - Mitigation for MDS and TAA vulnerability
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*
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* Clear CPU buffers if the corresponding static key is enabled
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*/
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static __always_inline void mds_user_clear_cpu_buffers(void)
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{
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if (static_branch_likely(&mds_user_clear))
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mds_clear_cpu_buffers();
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}
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/**
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* mds_idle_clear_cpu_buffers - Mitigation for MDS vulnerability
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*
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* Clear CPU buffers if the corresponding static key is enabled
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*/
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static inline void mds_idle_clear_cpu_buffers(void)
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{
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if (static_branch_likely(&mds_idle_clear))
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mds_clear_cpu_buffers();
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}
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#endif /* __ASSEMBLY__ */
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/*
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* Below is used in the eBPF JIT compiler and emits the byte sequence
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* for the following assembly:
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*
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* With retpolines configured:
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*
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* callq do_rop
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* spec_trap:
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* pause
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* lfence
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* jmp spec_trap
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* do_rop:
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* mov %rcx,(%rsp) for x86_64
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* mov %edx,(%esp) for x86_32
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* retq
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*
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* Without retpolines configured:
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*
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* jmp *%rcx for x86_64
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* jmp *%edx for x86_32
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*/
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#ifdef CONFIG_RETPOLINE
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# ifdef CONFIG_X86_64
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# define RETPOLINE_RCX_BPF_JIT_SIZE 17
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# define RETPOLINE_RCX_BPF_JIT() \
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do { \
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EMIT1_off32(0xE8, 7); /* callq do_rop */ \
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/* spec_trap: */ \
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EMIT2(0xF3, 0x90); /* pause */ \
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EMIT3(0x0F, 0xAE, 0xE8); /* lfence */ \
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EMIT2(0xEB, 0xF9); /* jmp spec_trap */ \
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/* do_rop: */ \
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EMIT4(0x48, 0x89, 0x0C, 0x24); /* mov %rcx,(%rsp) */ \
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EMIT1(0xC3); /* retq */ \
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} while (0)
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# else /* !CONFIG_X86_64 */
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# define RETPOLINE_EDX_BPF_JIT() \
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do { \
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EMIT1_off32(0xE8, 7); /* call do_rop */ \
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/* spec_trap: */ \
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EMIT2(0xF3, 0x90); /* pause */ \
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EMIT3(0x0F, 0xAE, 0xE8); /* lfence */ \
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EMIT2(0xEB, 0xF9); /* jmp spec_trap */ \
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/* do_rop: */ \
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EMIT3(0x89, 0x14, 0x24); /* mov %edx,(%esp) */ \
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EMIT1(0xC3); /* ret */ \
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} while (0)
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# endif
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#else /* !CONFIG_RETPOLINE */
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# ifdef CONFIG_X86_64
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# define RETPOLINE_RCX_BPF_JIT_SIZE 2
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# define RETPOLINE_RCX_BPF_JIT() \
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EMIT2(0xFF, 0xE1); /* jmp *%rcx */
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# else /* !CONFIG_X86_64 */
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# define RETPOLINE_EDX_BPF_JIT() \
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EMIT2(0xFF, 0xE2) /* jmp *%edx */
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# endif
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#endif
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#endif /* _ASM_X86_NOSPEC_BRANCH_H_ */
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