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![Linus Torvalds](/assets/img/avatar_default.png)
This series introduces preliminary ACPI 5.1 support to the arm64 kernel using the "hardware reduced" profile. We don't support any peripherals yet, so it's fairly limited in scope: - Memory init (UEFI) - ACPI discovery (RSDP via UEFI) - CPU init (FADT) - GIC init (MADT) - SMP boot (MADT + PSCI) - ACPI Kconfig options (dependent on EXPERT) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABCgAGBQJVNOC2AAoJELescNyEwWM08dIH/1Pn5xa04wwNDn0MOpbuQMk2 kHM7hx69fbXflTJpnZRVyFBjRxxr5qilA7rljAFLnFeF8Fcll/s5VNy7ElHKLISq CB0ywgUfOd/sFJH57rcc67pC1b/XuqTbE1u1NFwvp2R3j1kGAEJWNA6SyxIP4bbc NO5jScx0lQOJ3rrPAXBW8qlGkeUk7TPOQJtMrpftNXlFLFrR63rPaEmMZ9dWepBF aRE4GXPvyUhpyv5o9RvlN5l8bQttiRJ3f9QjyG7NYhX0PXH3DyvGUzYlk2IoZtID v3ssCQH3uRsAZHIBhaTyNqFnUIaDR825bvGqyG/tj2Dt3kQZiF+QrfnU5D9TuMw= =zLJn -----END PGP SIGNATURE----- Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull initial ACPI support for arm64 from Will Deacon: "This series introduces preliminary ACPI 5.1 support to the arm64 kernel using the "hardware reduced" profile. We don't support any peripherals yet, so it's fairly limited in scope: - MEMORY init (UEFI) - ACPI discovery (RSDP via UEFI) - CPU init (FADT) - GIC init (MADT) - SMP boot (MADT + PSCI) - ACPI Kconfig options (dependent on EXPERT) ACPI for arm64 has been in development for a while now and hardware has been available that can boot with either FDT or ACPI tables. This has been made possible by both changes to the ACPI spec to cater for ARM-based machines (known as "hardware-reduced" in ACPI parlance) but also a Linaro-driven effort to get this supported on top of the Linux kernel. This pull request is the result of that work. These changes allow us to initialise the CPUs, interrupt controller, and timers via ACPI tables, with memory information and cmdline coming from EFI. We don't support a hybrid ACPI/FDT scheme. Of course, there is still plenty of work to do (a serial console would be nice!) but I expect that to happen on a per-driver basis after this core series has been merged. Anyway, the diff stat here is fairly horrible, but splitting this up and merging it via all the different subsystems would have been extremely painful. Instead, we've got all the relevant Acks in place and I've not seen anything other than trivial (Kconfig) conflicts in -next (for completeness, I've included my resolution below). Nearly half of the insertions fall under Documentation/. So, we'll see how this goes. Right now, it all depends on EXPERT and I fully expect people to use FDT by default for the immediate future" * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (31 commits) ARM64 / ACPI: make acpi_map_gic_cpu_interface() as void function ARM64 / ACPI: Ignore the return error value of acpi_map_gic_cpu_interface() ARM64 / ACPI: fix usage of acpi_map_gic_cpu_interface ARM64: kernel: acpi: honour acpi=force command line parameter ARM64: kernel: acpi: refactor ACPI tables init and checks ARM64: kernel: psci: let ACPI probe PSCI version ARM64: kernel: psci: factor out probe function ACPI: move arm64 GSI IRQ model to generic GSI IRQ layer ARM64 / ACPI: Don't unflatten device tree if acpi=force is passed ARM64 / ACPI: additions of ACPI documentation for arm64 Documentation: ACPI for ARM64 ARM64 / ACPI: Enable ARM64 in Kconfig XEN / ACPI: Make XEN ACPI depend on X86 ARM64 / ACPI: Select ACPI_REDUCED_HARDWARE_ONLY if ACPI is enabled on ARM64 clocksource / arch_timer: Parse GTDT to initialize arch timer irqchip: Add GICv2 specific ACPI boot support ARM64 / ACPI: Introduce ACPI_IRQ_MODEL_GIC and register device's gsi ACPI / processor: Make it possible to get CPU hardware ID via GICC ACPI / processor: Introduce phys_cpuid_t for CPU hardware ID ARM64 / ACPI: Parse MADT for SMP initialization ...
884 lines
22 KiB
C
884 lines
22 KiB
C
/*
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* linux/drivers/clocksource/arm_arch_timer.c
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*
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* Copyright (C) 2011 ARM Ltd.
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <linux/smp.h>
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#include <linux/cpu.h>
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#include <linux/cpu_pm.h>
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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#include <linux/interrupt.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/sched_clock.h>
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#include <linux/acpi.h>
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#include <asm/arch_timer.h>
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#include <asm/virt.h>
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#include <clocksource/arm_arch_timer.h>
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#define CNTTIDR 0x08
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#define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4))
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#define CNTVCT_LO 0x08
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#define CNTVCT_HI 0x0c
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#define CNTFRQ 0x10
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#define CNTP_TVAL 0x28
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#define CNTP_CTL 0x2c
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#define CNTV_TVAL 0x38
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#define CNTV_CTL 0x3c
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#define ARCH_CP15_TIMER BIT(0)
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#define ARCH_MEM_TIMER BIT(1)
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static unsigned arch_timers_present __initdata;
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static void __iomem *arch_counter_base;
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struct arch_timer {
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void __iomem *base;
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struct clock_event_device evt;
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};
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#define to_arch_timer(e) container_of(e, struct arch_timer, evt)
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static u32 arch_timer_rate;
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enum ppi_nr {
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PHYS_SECURE_PPI,
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PHYS_NONSECURE_PPI,
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VIRT_PPI,
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HYP_PPI,
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MAX_TIMER_PPI
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};
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static int arch_timer_ppi[MAX_TIMER_PPI];
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static struct clock_event_device __percpu *arch_timer_evt;
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static bool arch_timer_use_virtual = true;
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static bool arch_timer_c3stop;
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static bool arch_timer_mem_use_virtual;
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/*
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* Architected system timer support.
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*/
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static __always_inline
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void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
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struct clock_event_device *clk)
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{
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if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
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struct arch_timer *timer = to_arch_timer(clk);
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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writel_relaxed(val, timer->base + CNTP_CTL);
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break;
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case ARCH_TIMER_REG_TVAL:
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writel_relaxed(val, timer->base + CNTP_TVAL);
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break;
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}
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} else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
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struct arch_timer *timer = to_arch_timer(clk);
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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writel_relaxed(val, timer->base + CNTV_CTL);
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break;
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case ARCH_TIMER_REG_TVAL:
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writel_relaxed(val, timer->base + CNTV_TVAL);
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break;
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}
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} else {
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arch_timer_reg_write_cp15(access, reg, val);
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}
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}
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static __always_inline
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u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
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struct clock_event_device *clk)
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{
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u32 val;
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if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
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struct arch_timer *timer = to_arch_timer(clk);
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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val = readl_relaxed(timer->base + CNTP_CTL);
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break;
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case ARCH_TIMER_REG_TVAL:
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val = readl_relaxed(timer->base + CNTP_TVAL);
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break;
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}
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} else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
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struct arch_timer *timer = to_arch_timer(clk);
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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val = readl_relaxed(timer->base + CNTV_CTL);
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break;
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case ARCH_TIMER_REG_TVAL:
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val = readl_relaxed(timer->base + CNTV_TVAL);
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break;
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}
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} else {
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val = arch_timer_reg_read_cp15(access, reg);
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}
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return val;
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}
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static __always_inline irqreturn_t timer_handler(const int access,
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struct clock_event_device *evt)
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{
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unsigned long ctrl;
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ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt);
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if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
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ctrl |= ARCH_TIMER_CTRL_IT_MASK;
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arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
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}
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static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
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}
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static irqreturn_t arch_timer_handler_phys_mem(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS, evt);
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}
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static irqreturn_t arch_timer_handler_virt_mem(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS, evt);
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}
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static __always_inline void timer_set_mode(const int access, int mode,
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struct clock_event_device *clk)
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{
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unsigned long ctrl;
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switch (mode) {
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
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ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
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arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
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break;
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default:
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break;
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}
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}
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static void arch_timer_set_mode_virt(enum clock_event_mode mode,
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struct clock_event_device *clk)
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{
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timer_set_mode(ARCH_TIMER_VIRT_ACCESS, mode, clk);
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}
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static void arch_timer_set_mode_phys(enum clock_event_mode mode,
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struct clock_event_device *clk)
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{
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timer_set_mode(ARCH_TIMER_PHYS_ACCESS, mode, clk);
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}
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static void arch_timer_set_mode_virt_mem(enum clock_event_mode mode,
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struct clock_event_device *clk)
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{
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timer_set_mode(ARCH_TIMER_MEM_VIRT_ACCESS, mode, clk);
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}
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static void arch_timer_set_mode_phys_mem(enum clock_event_mode mode,
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struct clock_event_device *clk)
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{
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timer_set_mode(ARCH_TIMER_MEM_PHYS_ACCESS, mode, clk);
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}
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static __always_inline void set_next_event(const int access, unsigned long evt,
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struct clock_event_device *clk)
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{
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unsigned long ctrl;
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ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
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ctrl |= ARCH_TIMER_CTRL_ENABLE;
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ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
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arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk);
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arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
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}
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static int arch_timer_set_next_event_virt(unsigned long evt,
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struct clock_event_device *clk)
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{
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set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
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return 0;
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}
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static int arch_timer_set_next_event_phys(unsigned long evt,
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struct clock_event_device *clk)
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{
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set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
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return 0;
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}
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static int arch_timer_set_next_event_virt_mem(unsigned long evt,
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struct clock_event_device *clk)
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{
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set_next_event(ARCH_TIMER_MEM_VIRT_ACCESS, evt, clk);
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return 0;
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}
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static int arch_timer_set_next_event_phys_mem(unsigned long evt,
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struct clock_event_device *clk)
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{
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set_next_event(ARCH_TIMER_MEM_PHYS_ACCESS, evt, clk);
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return 0;
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}
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static void __arch_timer_setup(unsigned type,
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struct clock_event_device *clk)
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{
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clk->features = CLOCK_EVT_FEAT_ONESHOT;
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if (type == ARCH_CP15_TIMER) {
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if (arch_timer_c3stop)
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clk->features |= CLOCK_EVT_FEAT_C3STOP;
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clk->name = "arch_sys_timer";
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clk->rating = 450;
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clk->cpumask = cpumask_of(smp_processor_id());
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if (arch_timer_use_virtual) {
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clk->irq = arch_timer_ppi[VIRT_PPI];
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clk->set_mode = arch_timer_set_mode_virt;
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clk->set_next_event = arch_timer_set_next_event_virt;
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} else {
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clk->irq = arch_timer_ppi[PHYS_SECURE_PPI];
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clk->set_mode = arch_timer_set_mode_phys;
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clk->set_next_event = arch_timer_set_next_event_phys;
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}
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} else {
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clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
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clk->name = "arch_mem_timer";
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clk->rating = 400;
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clk->cpumask = cpu_all_mask;
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if (arch_timer_mem_use_virtual) {
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clk->set_mode = arch_timer_set_mode_virt_mem;
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clk->set_next_event =
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arch_timer_set_next_event_virt_mem;
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} else {
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clk->set_mode = arch_timer_set_mode_phys_mem;
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clk->set_next_event =
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arch_timer_set_next_event_phys_mem;
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}
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}
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clk->set_mode(CLOCK_EVT_MODE_SHUTDOWN, clk);
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clockevents_config_and_register(clk, arch_timer_rate, 0xf, 0x7fffffff);
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}
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static void arch_timer_evtstrm_enable(int divider)
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{
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u32 cntkctl = arch_timer_get_cntkctl();
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cntkctl &= ~ARCH_TIMER_EVT_TRIGGER_MASK;
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/* Set the divider and enable virtual event stream */
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cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT)
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| ARCH_TIMER_VIRT_EVT_EN;
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arch_timer_set_cntkctl(cntkctl);
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elf_hwcap |= HWCAP_EVTSTRM;
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#ifdef CONFIG_COMPAT
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compat_elf_hwcap |= COMPAT_HWCAP_EVTSTRM;
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#endif
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}
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static void arch_timer_configure_evtstream(void)
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{
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int evt_stream_div, pos;
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/* Find the closest power of two to the divisor */
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evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ;
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pos = fls(evt_stream_div);
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if (pos > 1 && !(evt_stream_div & (1 << (pos - 2))))
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pos--;
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/* enable event stream */
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arch_timer_evtstrm_enable(min(pos, 15));
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}
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static void arch_counter_set_user_access(void)
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{
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u32 cntkctl = arch_timer_get_cntkctl();
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/* Disable user access to the timers and the physical counter */
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/* Also disable virtual event stream */
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cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN
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| ARCH_TIMER_USR_VT_ACCESS_EN
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| ARCH_TIMER_VIRT_EVT_EN
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| ARCH_TIMER_USR_PCT_ACCESS_EN);
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/* Enable user access to the virtual counter */
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cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN;
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arch_timer_set_cntkctl(cntkctl);
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}
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static int arch_timer_setup(struct clock_event_device *clk)
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{
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__arch_timer_setup(ARCH_CP15_TIMER, clk);
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if (arch_timer_use_virtual)
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enable_percpu_irq(arch_timer_ppi[VIRT_PPI], 0);
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else {
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enable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI], 0);
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if (arch_timer_ppi[PHYS_NONSECURE_PPI])
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enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], 0);
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}
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arch_counter_set_user_access();
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if (IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM))
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arch_timer_configure_evtstream();
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return 0;
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}
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static void
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arch_timer_detect_rate(void __iomem *cntbase, struct device_node *np)
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{
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/* Who has more than one independent system counter? */
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if (arch_timer_rate)
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return;
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/*
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* Try to determine the frequency from the device tree or CNTFRQ,
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* if ACPI is enabled, get the frequency from CNTFRQ ONLY.
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*/
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if (!acpi_disabled ||
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of_property_read_u32(np, "clock-frequency", &arch_timer_rate)) {
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if (cntbase)
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arch_timer_rate = readl_relaxed(cntbase + CNTFRQ);
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else
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arch_timer_rate = arch_timer_get_cntfrq();
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}
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/* Check the timer frequency. */
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if (arch_timer_rate == 0)
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pr_warn("Architected timer frequency not available\n");
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}
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static void arch_timer_banner(unsigned type)
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{
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pr_info("Architected %s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
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type & ARCH_CP15_TIMER ? "cp15" : "",
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type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? " and " : "",
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type & ARCH_MEM_TIMER ? "mmio" : "",
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(unsigned long)arch_timer_rate / 1000000,
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(unsigned long)(arch_timer_rate / 10000) % 100,
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type & ARCH_CP15_TIMER ?
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arch_timer_use_virtual ? "virt" : "phys" :
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"",
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type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? "/" : "",
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type & ARCH_MEM_TIMER ?
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arch_timer_mem_use_virtual ? "virt" : "phys" :
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"");
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}
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u32 arch_timer_get_rate(void)
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{
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return arch_timer_rate;
|
|
}
|
|
|
|
static u64 arch_counter_get_cntvct_mem(void)
|
|
{
|
|
u32 vct_lo, vct_hi, tmp_hi;
|
|
|
|
do {
|
|
vct_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
|
|
vct_lo = readl_relaxed(arch_counter_base + CNTVCT_LO);
|
|
tmp_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
|
|
} while (vct_hi != tmp_hi);
|
|
|
|
return ((u64) vct_hi << 32) | vct_lo;
|
|
}
|
|
|
|
/*
|
|
* Default to cp15 based access because arm64 uses this function for
|
|
* sched_clock() before DT is probed and the cp15 method is guaranteed
|
|
* to exist on arm64. arm doesn't use this before DT is probed so even
|
|
* if we don't have the cp15 accessors we won't have a problem.
|
|
*/
|
|
u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntvct;
|
|
|
|
static cycle_t arch_counter_read(struct clocksource *cs)
|
|
{
|
|
return arch_timer_read_counter();
|
|
}
|
|
|
|
static cycle_t arch_counter_read_cc(const struct cyclecounter *cc)
|
|
{
|
|
return arch_timer_read_counter();
|
|
}
|
|
|
|
static struct clocksource clocksource_counter = {
|
|
.name = "arch_sys_counter",
|
|
.rating = 400,
|
|
.read = arch_counter_read,
|
|
.mask = CLOCKSOURCE_MASK(56),
|
|
.flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP,
|
|
};
|
|
|
|
static struct cyclecounter cyclecounter = {
|
|
.read = arch_counter_read_cc,
|
|
.mask = CLOCKSOURCE_MASK(56),
|
|
};
|
|
|
|
static struct timecounter timecounter;
|
|
|
|
struct timecounter *arch_timer_get_timecounter(void)
|
|
{
|
|
return &timecounter;
|
|
}
|
|
|
|
static void __init arch_counter_register(unsigned type)
|
|
{
|
|
u64 start_count;
|
|
|
|
/* Register the CP15 based counter if we have one */
|
|
if (type & ARCH_CP15_TIMER) {
|
|
if (IS_ENABLED(CONFIG_ARM64) || arch_timer_use_virtual)
|
|
arch_timer_read_counter = arch_counter_get_cntvct;
|
|
else
|
|
arch_timer_read_counter = arch_counter_get_cntpct;
|
|
} else {
|
|
arch_timer_read_counter = arch_counter_get_cntvct_mem;
|
|
|
|
/* If the clocksource name is "arch_sys_counter" the
|
|
* VDSO will attempt to read the CP15-based counter.
|
|
* Ensure this does not happen when CP15-based
|
|
* counter is not available.
|
|
*/
|
|
clocksource_counter.name = "arch_mem_counter";
|
|
}
|
|
|
|
start_count = arch_timer_read_counter();
|
|
clocksource_register_hz(&clocksource_counter, arch_timer_rate);
|
|
cyclecounter.mult = clocksource_counter.mult;
|
|
cyclecounter.shift = clocksource_counter.shift;
|
|
timecounter_init(&timecounter, &cyclecounter, start_count);
|
|
|
|
/* 56 bits minimum, so we assume worst case rollover */
|
|
sched_clock_register(arch_timer_read_counter, 56, arch_timer_rate);
|
|
}
|
|
|
|
static void arch_timer_stop(struct clock_event_device *clk)
|
|
{
|
|
pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
|
|
clk->irq, smp_processor_id());
|
|
|
|
if (arch_timer_use_virtual)
|
|
disable_percpu_irq(arch_timer_ppi[VIRT_PPI]);
|
|
else {
|
|
disable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI]);
|
|
if (arch_timer_ppi[PHYS_NONSECURE_PPI])
|
|
disable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI]);
|
|
}
|
|
|
|
clk->set_mode(CLOCK_EVT_MODE_UNUSED, clk);
|
|
}
|
|
|
|
static int arch_timer_cpu_notify(struct notifier_block *self,
|
|
unsigned long action, void *hcpu)
|
|
{
|
|
/*
|
|
* Grab cpu pointer in each case to avoid spurious
|
|
* preemptible warnings
|
|
*/
|
|
switch (action & ~CPU_TASKS_FROZEN) {
|
|
case CPU_STARTING:
|
|
arch_timer_setup(this_cpu_ptr(arch_timer_evt));
|
|
break;
|
|
case CPU_DYING:
|
|
arch_timer_stop(this_cpu_ptr(arch_timer_evt));
|
|
break;
|
|
}
|
|
|
|
return NOTIFY_OK;
|
|
}
|
|
|
|
static struct notifier_block arch_timer_cpu_nb = {
|
|
.notifier_call = arch_timer_cpu_notify,
|
|
};
|
|
|
|
#ifdef CONFIG_CPU_PM
|
|
static unsigned int saved_cntkctl;
|
|
static int arch_timer_cpu_pm_notify(struct notifier_block *self,
|
|
unsigned long action, void *hcpu)
|
|
{
|
|
if (action == CPU_PM_ENTER)
|
|
saved_cntkctl = arch_timer_get_cntkctl();
|
|
else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT)
|
|
arch_timer_set_cntkctl(saved_cntkctl);
|
|
return NOTIFY_OK;
|
|
}
|
|
|
|
static struct notifier_block arch_timer_cpu_pm_notifier = {
|
|
.notifier_call = arch_timer_cpu_pm_notify,
|
|
};
|
|
|
|
static int __init arch_timer_cpu_pm_init(void)
|
|
{
|
|
return cpu_pm_register_notifier(&arch_timer_cpu_pm_notifier);
|
|
}
|
|
#else
|
|
static int __init arch_timer_cpu_pm_init(void)
|
|
{
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static int __init arch_timer_register(void)
|
|
{
|
|
int err;
|
|
int ppi;
|
|
|
|
arch_timer_evt = alloc_percpu(struct clock_event_device);
|
|
if (!arch_timer_evt) {
|
|
err = -ENOMEM;
|
|
goto out;
|
|
}
|
|
|
|
if (arch_timer_use_virtual) {
|
|
ppi = arch_timer_ppi[VIRT_PPI];
|
|
err = request_percpu_irq(ppi, arch_timer_handler_virt,
|
|
"arch_timer", arch_timer_evt);
|
|
} else {
|
|
ppi = arch_timer_ppi[PHYS_SECURE_PPI];
|
|
err = request_percpu_irq(ppi, arch_timer_handler_phys,
|
|
"arch_timer", arch_timer_evt);
|
|
if (!err && arch_timer_ppi[PHYS_NONSECURE_PPI]) {
|
|
ppi = arch_timer_ppi[PHYS_NONSECURE_PPI];
|
|
err = request_percpu_irq(ppi, arch_timer_handler_phys,
|
|
"arch_timer", arch_timer_evt);
|
|
if (err)
|
|
free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
|
|
arch_timer_evt);
|
|
}
|
|
}
|
|
|
|
if (err) {
|
|
pr_err("arch_timer: can't register interrupt %d (%d)\n",
|
|
ppi, err);
|
|
goto out_free;
|
|
}
|
|
|
|
err = register_cpu_notifier(&arch_timer_cpu_nb);
|
|
if (err)
|
|
goto out_free_irq;
|
|
|
|
err = arch_timer_cpu_pm_init();
|
|
if (err)
|
|
goto out_unreg_notify;
|
|
|
|
/* Immediately configure the timer on the boot CPU */
|
|
arch_timer_setup(this_cpu_ptr(arch_timer_evt));
|
|
|
|
return 0;
|
|
|
|
out_unreg_notify:
|
|
unregister_cpu_notifier(&arch_timer_cpu_nb);
|
|
out_free_irq:
|
|
if (arch_timer_use_virtual)
|
|
free_percpu_irq(arch_timer_ppi[VIRT_PPI], arch_timer_evt);
|
|
else {
|
|
free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
|
|
arch_timer_evt);
|
|
if (arch_timer_ppi[PHYS_NONSECURE_PPI])
|
|
free_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI],
|
|
arch_timer_evt);
|
|
}
|
|
|
|
out_free:
|
|
free_percpu(arch_timer_evt);
|
|
out:
|
|
return err;
|
|
}
|
|
|
|
static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq)
|
|
{
|
|
int ret;
|
|
irq_handler_t func;
|
|
struct arch_timer *t;
|
|
|
|
t = kzalloc(sizeof(*t), GFP_KERNEL);
|
|
if (!t)
|
|
return -ENOMEM;
|
|
|
|
t->base = base;
|
|
t->evt.irq = irq;
|
|
__arch_timer_setup(ARCH_MEM_TIMER, &t->evt);
|
|
|
|
if (arch_timer_mem_use_virtual)
|
|
func = arch_timer_handler_virt_mem;
|
|
else
|
|
func = arch_timer_handler_phys_mem;
|
|
|
|
ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &t->evt);
|
|
if (ret) {
|
|
pr_err("arch_timer: Failed to request mem timer irq\n");
|
|
kfree(t);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct of_device_id arch_timer_of_match[] __initconst = {
|
|
{ .compatible = "arm,armv7-timer", },
|
|
{ .compatible = "arm,armv8-timer", },
|
|
{},
|
|
};
|
|
|
|
static const struct of_device_id arch_timer_mem_of_match[] __initconst = {
|
|
{ .compatible = "arm,armv7-timer-mem", },
|
|
{},
|
|
};
|
|
|
|
static bool __init
|
|
arch_timer_needs_probing(int type, const struct of_device_id *matches)
|
|
{
|
|
struct device_node *dn;
|
|
bool needs_probing = false;
|
|
|
|
dn = of_find_matching_node(NULL, matches);
|
|
if (dn && of_device_is_available(dn) && !(arch_timers_present & type))
|
|
needs_probing = true;
|
|
of_node_put(dn);
|
|
|
|
return needs_probing;
|
|
}
|
|
|
|
static void __init arch_timer_common_init(void)
|
|
{
|
|
unsigned mask = ARCH_CP15_TIMER | ARCH_MEM_TIMER;
|
|
|
|
/* Wait until both nodes are probed if we have two timers */
|
|
if ((arch_timers_present & mask) != mask) {
|
|
if (arch_timer_needs_probing(ARCH_MEM_TIMER, arch_timer_mem_of_match))
|
|
return;
|
|
if (arch_timer_needs_probing(ARCH_CP15_TIMER, arch_timer_of_match))
|
|
return;
|
|
}
|
|
|
|
arch_timer_banner(arch_timers_present);
|
|
arch_counter_register(arch_timers_present);
|
|
arch_timer_arch_init();
|
|
}
|
|
|
|
static void __init arch_timer_init(void)
|
|
{
|
|
/*
|
|
* If HYP mode is available, we know that the physical timer
|
|
* has been configured to be accessible from PL1. Use it, so
|
|
* that a guest can use the virtual timer instead.
|
|
*
|
|
* If no interrupt provided for virtual timer, we'll have to
|
|
* stick to the physical timer. It'd better be accessible...
|
|
*/
|
|
if (is_hyp_mode_available() || !arch_timer_ppi[VIRT_PPI]) {
|
|
arch_timer_use_virtual = false;
|
|
|
|
if (!arch_timer_ppi[PHYS_SECURE_PPI] ||
|
|
!arch_timer_ppi[PHYS_NONSECURE_PPI]) {
|
|
pr_warn("arch_timer: No interrupt available, giving up\n");
|
|
return;
|
|
}
|
|
}
|
|
|
|
arch_timer_register();
|
|
arch_timer_common_init();
|
|
}
|
|
|
|
static void __init arch_timer_of_init(struct device_node *np)
|
|
{
|
|
int i;
|
|
|
|
if (arch_timers_present & ARCH_CP15_TIMER) {
|
|
pr_warn("arch_timer: multiple nodes in dt, skipping\n");
|
|
return;
|
|
}
|
|
|
|
arch_timers_present |= ARCH_CP15_TIMER;
|
|
for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++)
|
|
arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
|
|
|
|
arch_timer_detect_rate(NULL, np);
|
|
|
|
arch_timer_c3stop = !of_property_read_bool(np, "always-on");
|
|
|
|
/*
|
|
* If we cannot rely on firmware initializing the timer registers then
|
|
* we should use the physical timers instead.
|
|
*/
|
|
if (IS_ENABLED(CONFIG_ARM) &&
|
|
of_property_read_bool(np, "arm,cpu-registers-not-fw-configured"))
|
|
arch_timer_use_virtual = false;
|
|
|
|
arch_timer_init();
|
|
}
|
|
CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init);
|
|
CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init);
|
|
|
|
static void __init arch_timer_mem_init(struct device_node *np)
|
|
{
|
|
struct device_node *frame, *best_frame = NULL;
|
|
void __iomem *cntctlbase, *base;
|
|
unsigned int irq;
|
|
u32 cnttidr;
|
|
|
|
arch_timers_present |= ARCH_MEM_TIMER;
|
|
cntctlbase = of_iomap(np, 0);
|
|
if (!cntctlbase) {
|
|
pr_err("arch_timer: Can't find CNTCTLBase\n");
|
|
return;
|
|
}
|
|
|
|
cnttidr = readl_relaxed(cntctlbase + CNTTIDR);
|
|
iounmap(cntctlbase);
|
|
|
|
/*
|
|
* Try to find a virtual capable frame. Otherwise fall back to a
|
|
* physical capable frame.
|
|
*/
|
|
for_each_available_child_of_node(np, frame) {
|
|
int n;
|
|
|
|
if (of_property_read_u32(frame, "frame-number", &n)) {
|
|
pr_err("arch_timer: Missing frame-number\n");
|
|
of_node_put(best_frame);
|
|
of_node_put(frame);
|
|
return;
|
|
}
|
|
|
|
if (cnttidr & CNTTIDR_VIRT(n)) {
|
|
of_node_put(best_frame);
|
|
best_frame = frame;
|
|
arch_timer_mem_use_virtual = true;
|
|
break;
|
|
}
|
|
of_node_put(best_frame);
|
|
best_frame = of_node_get(frame);
|
|
}
|
|
|
|
base = arch_counter_base = of_iomap(best_frame, 0);
|
|
if (!base) {
|
|
pr_err("arch_timer: Can't map frame's registers\n");
|
|
of_node_put(best_frame);
|
|
return;
|
|
}
|
|
|
|
if (arch_timer_mem_use_virtual)
|
|
irq = irq_of_parse_and_map(best_frame, 1);
|
|
else
|
|
irq = irq_of_parse_and_map(best_frame, 0);
|
|
of_node_put(best_frame);
|
|
if (!irq) {
|
|
pr_err("arch_timer: Frame missing %s irq",
|
|
arch_timer_mem_use_virtual ? "virt" : "phys");
|
|
return;
|
|
}
|
|
|
|
arch_timer_detect_rate(base, np);
|
|
arch_timer_mem_register(base, irq);
|
|
arch_timer_common_init();
|
|
}
|
|
CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
|
|
arch_timer_mem_init);
|
|
|
|
#ifdef CONFIG_ACPI
|
|
static int __init map_generic_timer_interrupt(u32 interrupt, u32 flags)
|
|
{
|
|
int trigger, polarity;
|
|
|
|
if (!interrupt)
|
|
return 0;
|
|
|
|
trigger = (flags & ACPI_GTDT_INTERRUPT_MODE) ? ACPI_EDGE_SENSITIVE
|
|
: ACPI_LEVEL_SENSITIVE;
|
|
|
|
polarity = (flags & ACPI_GTDT_INTERRUPT_POLARITY) ? ACPI_ACTIVE_LOW
|
|
: ACPI_ACTIVE_HIGH;
|
|
|
|
return acpi_register_gsi(NULL, interrupt, trigger, polarity);
|
|
}
|
|
|
|
/* Initialize per-processor generic timer */
|
|
static int __init arch_timer_acpi_init(struct acpi_table_header *table)
|
|
{
|
|
struct acpi_table_gtdt *gtdt;
|
|
|
|
if (arch_timers_present & ARCH_CP15_TIMER) {
|
|
pr_warn("arch_timer: already initialized, skipping\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
gtdt = container_of(table, struct acpi_table_gtdt, header);
|
|
|
|
arch_timers_present |= ARCH_CP15_TIMER;
|
|
|
|
arch_timer_ppi[PHYS_SECURE_PPI] =
|
|
map_generic_timer_interrupt(gtdt->secure_el1_interrupt,
|
|
gtdt->secure_el1_flags);
|
|
|
|
arch_timer_ppi[PHYS_NONSECURE_PPI] =
|
|
map_generic_timer_interrupt(gtdt->non_secure_el1_interrupt,
|
|
gtdt->non_secure_el1_flags);
|
|
|
|
arch_timer_ppi[VIRT_PPI] =
|
|
map_generic_timer_interrupt(gtdt->virtual_timer_interrupt,
|
|
gtdt->virtual_timer_flags);
|
|
|
|
arch_timer_ppi[HYP_PPI] =
|
|
map_generic_timer_interrupt(gtdt->non_secure_el2_interrupt,
|
|
gtdt->non_secure_el2_flags);
|
|
|
|
/* Get the frequency from CNTFRQ */
|
|
arch_timer_detect_rate(NULL, NULL);
|
|
|
|
/* Always-on capability */
|
|
arch_timer_c3stop = !(gtdt->non_secure_el1_flags & ACPI_GTDT_ALWAYS_ON);
|
|
|
|
arch_timer_init();
|
|
return 0;
|
|
}
|
|
|
|
/* Initialize all the generic timers presented in GTDT */
|
|
void __init acpi_generic_timer_init(void)
|
|
{
|
|
if (acpi_disabled)
|
|
return;
|
|
|
|
acpi_table_parse(ACPI_SIG_GTDT, arch_timer_acpi_init);
|
|
}
|
|
#endif
|