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![Carlo Caione](/assets/img/avatar_default.png)
Meson6 SoCs are equipped with 5 32-bit timers, called TIMER_A, TIMER_B, TIMER_C, TIMER_D and TIMER_E. The driver is providing clocksource support for the 32-bit counter using TIMER_E. Clockevents are also supported using TIMER_A. Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Carlo Caione <carlo@caione.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
167 lines
4.3 KiB
C
167 lines
4.3 KiB
C
/*
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* Amlogic Meson6 SoCs timer handling.
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*
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* Copyright (C) 2014 Carlo Caione <carlo@caione.org>
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*
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* Based on code from Amlogic, Inc
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqreturn.h>
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#include <linux/sched_clock.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#define CED_ID 0
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#define CSD_ID 4
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#define TIMER_ISA_MUX 0
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#define TIMER_ISA_VAL(t) (((t) + 1) << 2)
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#define TIMER_INPUT_BIT(t) (2 * (t))
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#define TIMER_ENABLE_BIT(t) (16 + (t))
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#define TIMER_PERIODIC_BIT(t) (12 + (t))
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#define TIMER_CED_INPUT_MASK (3UL << TIMER_INPUT_BIT(CED_ID))
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#define TIMER_CSD_INPUT_MASK (7UL << TIMER_INPUT_BIT(CSD_ID))
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#define TIMER_CED_UNIT_1US 0
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#define TIMER_CSD_UNIT_1US 1
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static void __iomem *timer_base;
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static u64 notrace meson6_timer_sched_read(void)
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{
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return (u64)readl(timer_base + TIMER_ISA_VAL(CSD_ID));
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}
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static void meson6_clkevt_time_stop(unsigned char timer)
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{
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u32 val = readl(timer_base + TIMER_ISA_MUX);
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writel(val & ~TIMER_ENABLE_BIT(timer), timer_base + TIMER_ISA_MUX);
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}
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static void meson6_clkevt_time_setup(unsigned char timer, unsigned long delay)
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{
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writel(delay, timer_base + TIMER_ISA_VAL(timer));
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}
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static void meson6_clkevt_time_start(unsigned char timer, bool periodic)
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{
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u32 val = readl(timer_base + TIMER_ISA_MUX);
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if (periodic)
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val |= TIMER_PERIODIC_BIT(timer);
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else
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val &= ~TIMER_PERIODIC_BIT(timer);
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writel(val | TIMER_ENABLE_BIT(timer), timer_base + TIMER_ISA_MUX);
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}
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static void meson6_clkevt_mode(enum clock_event_mode mode,
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struct clock_event_device *clk)
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{
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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meson6_clkevt_time_stop(CED_ID);
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meson6_clkevt_time_setup(CED_ID, USEC_PER_SEC/HZ - 1);
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meson6_clkevt_time_start(CED_ID, true);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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meson6_clkevt_time_stop(CED_ID);
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meson6_clkevt_time_start(CED_ID, false);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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default:
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meson6_clkevt_time_stop(CED_ID);
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break;
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}
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}
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static int meson6_clkevt_next_event(unsigned long evt,
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struct clock_event_device *unused)
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{
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meson6_clkevt_time_stop(CED_ID);
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meson6_clkevt_time_setup(CED_ID, evt);
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meson6_clkevt_time_start(CED_ID, false);
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return 0;
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}
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static struct clock_event_device meson6_clockevent = {
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.name = "meson6_tick",
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.rating = 400,
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_mode = meson6_clkevt_mode,
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.set_next_event = meson6_clkevt_next_event,
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};
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static irqreturn_t meson6_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = (struct clock_event_device *)dev_id;
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction meson6_timer_irq = {
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.name = "meson6_timer",
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.flags = IRQF_TIMER | IRQF_IRQPOLL,
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.handler = meson6_timer_interrupt,
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.dev_id = &meson6_clockevent,
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};
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static void __init meson6_timer_init(struct device_node *node)
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{
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u32 val;
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int ret, irq;
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timer_base = of_io_request_and_map(node, 0, "meson6-timer");
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if (IS_ERR(timer_base))
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panic("Can't map registers");
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irq = irq_of_parse_and_map(node, 0);
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if (irq <= 0)
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panic("Can't parse IRQ");
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/* Set 1us for timer E */
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val = readl(timer_base + TIMER_ISA_MUX);
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val &= ~TIMER_CSD_INPUT_MASK;
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val |= TIMER_CSD_UNIT_1US << TIMER_INPUT_BIT(CSD_ID);
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writel(val, timer_base + TIMER_ISA_MUX);
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sched_clock_register(meson6_timer_sched_read, 32, USEC_PER_SEC);
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clocksource_mmio_init(timer_base + TIMER_ISA_VAL(CSD_ID), node->name,
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1000 * 1000, 300, 32, clocksource_mmio_readl_up);
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/* Timer A base 1us */
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val &= ~TIMER_CED_INPUT_MASK;
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val |= TIMER_CED_UNIT_1US << TIMER_INPUT_BIT(CED_ID);
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writel(val, timer_base + TIMER_ISA_MUX);
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/* Stop the timer A */
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meson6_clkevt_time_stop(CED_ID);
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ret = setup_irq(irq, &meson6_timer_irq);
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if (ret)
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pr_warn("failed to setup irq %d\n", irq);
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meson6_clockevent.cpumask = cpu_possible_mask;
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meson6_clockevent.irq = irq;
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clockevents_config_and_register(&meson6_clockevent, USEC_PER_SEC,
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1, 0xfffe);
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}
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CLOCKSOURCE_OF_DECLARE(meson6, "amlogic,meson6-timer",
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meson6_timer_init);
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