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![Matthias Brugger](/assets/img/avatar_default.png)
We have two race conditions in the probe code which could lead to a null pointer dereference in the interrupt handler. The interrupt handler accesses the clockevent device, which may not yet be registered. First race condition happens when the interrupt handler gets registered before the interrupts get disabled. The second race condition happens when the interrupts get enabled, but the clockevent device is not yet registered. Fix that by disabling the interrupts before we register the interrupt and enable the interrupts after the clockevent device got registered. Reported-by: Gongbae Park <yongbae2@gmail.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Cc: stable@vger.kernel.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
262 lines
6.8 KiB
C
262 lines
6.8 KiB
C
/*
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* Mediatek SoCs General-Purpose Timer handling.
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*
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* Copyright (C) 2014 Matthias Brugger
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*
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* Matthias Brugger <matthias.bgg@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqreturn.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/slab.h>
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#define GPT_IRQ_EN_REG 0x00
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#define GPT_IRQ_ENABLE(val) BIT((val) - 1)
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#define GPT_IRQ_ACK_REG 0x08
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#define GPT_IRQ_ACK(val) BIT((val) - 1)
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#define TIMER_CTRL_REG(val) (0x10 * (val))
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#define TIMER_CTRL_OP(val) (((val) & 0x3) << 4)
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#define TIMER_CTRL_OP_ONESHOT (0)
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#define TIMER_CTRL_OP_REPEAT (1)
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#define TIMER_CTRL_OP_FREERUN (3)
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#define TIMER_CTRL_CLEAR (2)
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#define TIMER_CTRL_ENABLE (1)
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#define TIMER_CTRL_DISABLE (0)
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#define TIMER_CLK_REG(val) (0x04 + (0x10 * (val)))
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#define TIMER_CLK_SRC(val) (((val) & 0x1) << 4)
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#define TIMER_CLK_SRC_SYS13M (0)
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#define TIMER_CLK_SRC_RTC32K (1)
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#define TIMER_CLK_DIV1 (0x0)
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#define TIMER_CLK_DIV2 (0x1)
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#define TIMER_CNT_REG(val) (0x08 + (0x10 * (val)))
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#define TIMER_CMP_REG(val) (0x0C + (0x10 * (val)))
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#define GPT_CLK_EVT 1
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#define GPT_CLK_SRC 2
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struct mtk_clock_event_device {
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void __iomem *gpt_base;
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u32 ticks_per_jiffy;
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struct clock_event_device dev;
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};
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static inline struct mtk_clock_event_device *to_mtk_clk(
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struct clock_event_device *c)
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{
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return container_of(c, struct mtk_clock_event_device, dev);
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}
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static void mtk_clkevt_time_stop(struct mtk_clock_event_device *evt, u8 timer)
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{
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u32 val;
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val = readl(evt->gpt_base + TIMER_CTRL_REG(timer));
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writel(val & ~TIMER_CTRL_ENABLE, evt->gpt_base +
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TIMER_CTRL_REG(timer));
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}
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static void mtk_clkevt_time_setup(struct mtk_clock_event_device *evt,
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unsigned long delay, u8 timer)
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{
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writel(delay, evt->gpt_base + TIMER_CMP_REG(timer));
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}
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static void mtk_clkevt_time_start(struct mtk_clock_event_device *evt,
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bool periodic, u8 timer)
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{
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u32 val;
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/* Acknowledge interrupt */
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writel(GPT_IRQ_ACK(timer), evt->gpt_base + GPT_IRQ_ACK_REG);
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val = readl(evt->gpt_base + TIMER_CTRL_REG(timer));
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/* Clear 2 bit timer operation mode field */
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val &= ~TIMER_CTRL_OP(0x3);
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if (periodic)
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val |= TIMER_CTRL_OP(TIMER_CTRL_OP_REPEAT);
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else
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val |= TIMER_CTRL_OP(TIMER_CTRL_OP_ONESHOT);
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writel(val | TIMER_CTRL_ENABLE | TIMER_CTRL_CLEAR,
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evt->gpt_base + TIMER_CTRL_REG(timer));
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}
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static void mtk_clkevt_mode(enum clock_event_mode mode,
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struct clock_event_device *clk)
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{
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struct mtk_clock_event_device *evt = to_mtk_clk(clk);
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mtk_clkevt_time_stop(evt, GPT_CLK_EVT);
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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mtk_clkevt_time_setup(evt, evt->ticks_per_jiffy, GPT_CLK_EVT);
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mtk_clkevt_time_start(evt, true, GPT_CLK_EVT);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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/* Timer is enabled in set_next_event */
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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default:
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/* No more interrupts will occur as source is disabled */
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break;
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}
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}
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static int mtk_clkevt_next_event(unsigned long event,
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struct clock_event_device *clk)
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{
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struct mtk_clock_event_device *evt = to_mtk_clk(clk);
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mtk_clkevt_time_stop(evt, GPT_CLK_EVT);
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mtk_clkevt_time_setup(evt, event, GPT_CLK_EVT);
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mtk_clkevt_time_start(evt, false, GPT_CLK_EVT);
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return 0;
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}
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static irqreturn_t mtk_timer_interrupt(int irq, void *dev_id)
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{
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struct mtk_clock_event_device *evt = dev_id;
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/* Acknowledge timer0 irq */
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writel(GPT_IRQ_ACK(GPT_CLK_EVT), evt->gpt_base + GPT_IRQ_ACK_REG);
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evt->dev.event_handler(&evt->dev);
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return IRQ_HANDLED;
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}
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static void mtk_timer_global_reset(struct mtk_clock_event_device *evt)
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{
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/* Disable all interrupts */
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writel(0x0, evt->gpt_base + GPT_IRQ_EN_REG);
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/* Acknowledge all interrupts */
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writel(0x3f, evt->gpt_base + GPT_IRQ_ACK_REG);
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}
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static void
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mtk_timer_setup(struct mtk_clock_event_device *evt, u8 timer, u8 option)
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{
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writel(TIMER_CTRL_CLEAR | TIMER_CTRL_DISABLE,
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evt->gpt_base + TIMER_CTRL_REG(timer));
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writel(TIMER_CLK_SRC(TIMER_CLK_SRC_SYS13M) | TIMER_CLK_DIV1,
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evt->gpt_base + TIMER_CLK_REG(timer));
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writel(0x0, evt->gpt_base + TIMER_CMP_REG(timer));
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writel(TIMER_CTRL_OP(option) | TIMER_CTRL_ENABLE,
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evt->gpt_base + TIMER_CTRL_REG(timer));
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}
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static void mtk_timer_enable_irq(struct mtk_clock_event_device *evt, u8 timer)
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{
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u32 val;
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val = readl(evt->gpt_base + GPT_IRQ_EN_REG);
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writel(val | GPT_IRQ_ENABLE(timer),
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evt->gpt_base + GPT_IRQ_EN_REG);
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}
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static void __init mtk_timer_init(struct device_node *node)
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{
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struct mtk_clock_event_device *evt;
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struct resource res;
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unsigned long rate = 0;
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struct clk *clk;
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evt = kzalloc(sizeof(*evt), GFP_KERNEL);
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if (!evt) {
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pr_warn("Can't allocate mtk clock event driver struct");
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return;
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}
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evt->dev.name = "mtk_tick";
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evt->dev.rating = 300;
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evt->dev.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
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evt->dev.set_mode = mtk_clkevt_mode;
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evt->dev.set_next_event = mtk_clkevt_next_event;
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evt->dev.cpumask = cpu_possible_mask;
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evt->gpt_base = of_io_request_and_map(node, 0, "mtk-timer");
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if (IS_ERR(evt->gpt_base)) {
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pr_warn("Can't get resource\n");
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return;
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}
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evt->dev.irq = irq_of_parse_and_map(node, 0);
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if (evt->dev.irq <= 0) {
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pr_warn("Can't parse IRQ");
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goto err_mem;
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}
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clk = of_clk_get(node, 0);
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if (IS_ERR(clk)) {
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pr_warn("Can't get timer clock");
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goto err_irq;
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}
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if (clk_prepare_enable(clk)) {
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pr_warn("Can't prepare clock");
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goto err_clk_put;
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}
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rate = clk_get_rate(clk);
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mtk_timer_global_reset(evt);
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if (request_irq(evt->dev.irq, mtk_timer_interrupt,
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IRQF_TIMER | IRQF_IRQPOLL, "mtk_timer", evt)) {
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pr_warn("failed to setup irq %d\n", evt->dev.irq);
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goto err_clk_disable;
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}
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evt->ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
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/* Configure clock source */
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mtk_timer_setup(evt, GPT_CLK_SRC, TIMER_CTRL_OP_FREERUN);
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clocksource_mmio_init(evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC),
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node->name, rate, 300, 32, clocksource_mmio_readl_up);
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/* Configure clock event */
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mtk_timer_setup(evt, GPT_CLK_EVT, TIMER_CTRL_OP_REPEAT);
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clockevents_config_and_register(&evt->dev, rate, 0x3,
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0xffffffff);
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mtk_timer_enable_irq(evt, GPT_CLK_EVT);
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return;
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err_clk_disable:
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clk_disable_unprepare(clk);
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err_clk_put:
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clk_put(clk);
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err_irq:
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irq_dispose_mapping(evt->dev.irq);
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err_mem:
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iounmap(evt->gpt_base);
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of_address_to_resource(node, 0, &res);
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release_mem_region(res.start, resource_size(&res));
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}
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CLOCKSOURCE_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_timer_init);
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