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linux-stable/arch/arm64/boot/dts/mediatek/mt8195-demo.dts

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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2022 BayLibre, SAS.
* Author: Fabien Parent <fparent@baylibre.com>
*/
/dts-v1/;
#include "mt8195.dtsi"
#include "mt6359.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
#include <dt-bindings/regulator/mediatek,mt6360-regulator.h>
/ {
model = "MediaTek MT8195 demo board";
compatible = "mediatek,mt8195-demo", "mediatek,mt8195";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:921600n8";
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&gpio_keys_pins>;
key-0 {
gpios = <&pio 106 GPIO_ACTIVE_LOW>;
label = "volume_up";
linux,code = <KEY_VOLUMEUP>;
wakeup-source;
debounce-interval = <15>;
};
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0x2 0x00000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/*
* 12 MiB reserved for OP-TEE (BL32)
* +-----------------------+ 0x43e0_0000
* | SHMEM 2MiB |
* +-----------------------+ 0x43c0_0000
* | | TA_RAM 8MiB |
* + TZDRAM +--------------+ 0x4340_0000
* | | TEE_RAM 2MiB |
* +-----------------------+ 0x4320_0000
*/
optee_reserved: optee@43200000 {
no-map;
reg = <0 0x43200000 0 0x00c00000>;
};
scp_mem: memory@50000000 {
compatible = "shared-dma-pool";
reg = <0 0x50000000 0 0x2900000>;
no-map;
};
vpu_mem: memory@53000000 {
compatible = "shared-dma-pool";
reg = <0 0x53000000 0 0x1400000>; /* 20 MB */
};
/* 2 MiB reserved for ARM Trusted Firmware (BL31) */
bl31_secmon_mem: memory@54600000 {
no-map;
reg = <0 0x54600000 0x0 0x200000>;
};
snd_dma_mem: memory@60000000 {
compatible = "shared-dma-pool";
reg = <0 0x60000000 0 0x1100000>;
no-map;
};
apu_mem: memory@62000000 {
compatible = "shared-dma-pool";
reg = <0 0x62000000 0 0x1400000>; /* 20 MB */
};
};
};
&eth {
phy-mode = "rgmii-id";
phy-handle = <&ethernet_phy0>;
snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>;
snps,reset-delays-us = <0 10000 80000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&eth_default_pins>;
pinctrl-1 = <&eth_sleep_pins>;
status = "okay";
mdio {
ethernet_phy0: ethernet-phy@1 {
reg = <0x1>;
};
};
};
&i2c6 {
clock-frequency = <400000>;
pinctrl-0 = <&i2c6_pins>;
pinctrl-names = "default";
status = "okay";
mt6360: pmic@34 {
compatible = "mediatek,mt6360";
reg = <0x34>;
interrupt-controller;
#interrupt-cells = <1>;
interrupts-extended = <&pio 101 IRQ_TYPE_EDGE_FALLING>;
interrupt-names = "IRQB";
charger {
compatible = "mediatek,mt6360-chg";
richtek,vinovp-microvolt = <14500000>;
otg_vbus_regulator: usb-otg-vbus-regulator {
regulator-compatible = "usb-otg-vbus";
regulator-name = "usb-otg-vbus";
regulator-min-microvolt = <4425000>;
regulator-max-microvolt = <5825000>;
};
};
regulator {
compatible = "mediatek,mt6360-regulator";
LDO_VIN3-supply = <&mt6360_buck2>;
mt6360_buck1: buck1 {
regulator-compatible = "BUCK1";
regulator-name = "mt6360,buck1";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1300000>;
regulator-allowed-modes = <MT6360_OPMODE_NORMAL
MT6360_OPMODE_LP
MT6360_OPMODE_ULP>;
regulator-always-on;
};
mt6360_buck2: buck2 {
regulator-compatible = "BUCK2";
regulator-name = "mt6360,buck2";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1300000>;
regulator-allowed-modes = <MT6360_OPMODE_NORMAL
MT6360_OPMODE_LP
MT6360_OPMODE_ULP>;
regulator-always-on;
};
mt6360_ldo1: ldo1 {
regulator-compatible = "LDO1";
regulator-name = "mt6360,ldo1";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-allowed-modes = <MT6360_OPMODE_NORMAL
MT6360_OPMODE_LP>;
};
mt6360_ldo2: ldo2 {
regulator-compatible = "LDO2";
regulator-name = "mt6360,ldo2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-allowed-modes = <MT6360_OPMODE_NORMAL
MT6360_OPMODE_LP>;
};
mt6360_ldo3: ldo3 {
regulator-compatible = "LDO3";
regulator-name = "mt6360,ldo3";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-allowed-modes = <MT6360_OPMODE_NORMAL
MT6360_OPMODE_LP>;
};
mt6360_ldo5: ldo5 {
regulator-compatible = "LDO5";
regulator-name = "mt6360,ldo5";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3600000>;
regulator-allowed-modes = <MT6360_OPMODE_NORMAL
MT6360_OPMODE_LP>;
};
mt6360_ldo6: ldo6 {
regulator-compatible = "LDO6";
regulator-name = "mt6360,ldo6";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <2100000>;
regulator-allowed-modes = <MT6360_OPMODE_NORMAL
MT6360_OPMODE_LP>;
};
mt6360_ldo7: ldo7 {
regulator-compatible = "LDO7";
regulator-name = "mt6360,ldo7";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <2100000>;
regulator-allowed-modes = <MT6360_OPMODE_NORMAL
MT6360_OPMODE_LP>;
regulator-always-on;
};
};
};
};
&mmc0 {
status = "okay";
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc0_default_pins>;
pinctrl-1 = <&mmc0_uhs_pins>;
bus-width = <8>;
max-frequency = <200000000>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
cap-mmc-hw-reset;
no-sdio;
no-sd;
hs400-ds-delay = <0x14c11>;
vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
vqmmc-supply = <&mt6359_vufs_ldo_reg>;
non-removable;
};
&mmc1 {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc1_default_pins>;
pinctrl-1 = <&mmc1_uhs_pins>;
cd-gpios = <&pio 129 GPIO_ACTIVE_LOW>;
bus-width = <4>;
max-frequency = <200000000>;
cap-sd-highspeed;
sd-uhs-sdr50;
sd-uhs-sdr104;
vmmc-supply = <&mt6360_ldo5>;
vqmmc-supply = <&mt6360_ldo3>;
status = "okay";
};
&mt6359_vbbck_ldo_reg {
regulator-always-on;
};
&mt6359_vcore_buck_reg {
regulator-always-on;
};
&mt6359_vgpu11_buck_reg {
regulator-always-on;
};
&mt6359_vproc1_buck_reg {
regulator-always-on;
};
&mt6359_vproc2_buck_reg {
regulator-always-on;
};
&mt6359_vpu_buck_reg {
regulator-always-on;
};
&mt6359_vrf12_ldo_reg {
regulator-always-on;
};
&mt6359_vsram_md_ldo_reg {
regulator-always-on;
};
&mt6359_vsram_others_ldo_reg {
regulator-always-on;
};
&pio {
eth_default_pins: eth-default-pins {
pins-txd {
pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>,
<PINMUX_GPIO78__FUNC_GBE_TXD2>,
<PINMUX_GPIO79__FUNC_GBE_TXD1>,
<PINMUX_GPIO80__FUNC_GBE_TXD0>;
drive-strength = <MTK_DRIVE_8mA>;
};
pins-cc {
pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>,
<PINMUX_GPIO88__FUNC_GBE_TXEN>,
<PINMUX_GPIO87__FUNC_GBE_RXDV>,
<PINMUX_GPIO86__FUNC_GBE_RXC>;
drive-strength = <MTK_DRIVE_8mA>;
};
pins-rxd {
pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>,
<PINMUX_GPIO82__FUNC_GBE_RXD2>,
<PINMUX_GPIO83__FUNC_GBE_RXD1>,
<PINMUX_GPIO84__FUNC_GBE_RXD0>;
};
pins-mdio {
pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>,
<PINMUX_GPIO90__FUNC_GBE_MDIO>;
input-enable;
};
pins-power {
pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
<PINMUX_GPIO92__FUNC_GPIO92>;
output-high;
};
};
eth_sleep_pins: eth-sleep-pins {
pins-txd {
pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
<PINMUX_GPIO78__FUNC_GPIO78>,
<PINMUX_GPIO79__FUNC_GPIO79>,
<PINMUX_GPIO80__FUNC_GPIO80>;
};
pins-cc {
pinmux = <PINMUX_GPIO85__FUNC_GPIO85>,
<PINMUX_GPIO88__FUNC_GPIO88>,
<PINMUX_GPIO87__FUNC_GPIO87>,
<PINMUX_GPIO86__FUNC_GPIO86>;
};
pins-rxd {
pinmux = <PINMUX_GPIO81__FUNC_GPIO81>,
<PINMUX_GPIO82__FUNC_GPIO82>,
<PINMUX_GPIO83__FUNC_GPIO83>,
<PINMUX_GPIO84__FUNC_GPIO84>;
};
pins-mdio {
pinmux = <PINMUX_GPIO89__FUNC_GPIO89>,
<PINMUX_GPIO90__FUNC_GPIO90>;
input-disable;
bias-disable;
};
};
gpio_keys_pins: gpio-keys-pins {
pins {
pinmux = <PINMUX_GPIO106__FUNC_GPIO106>;
input-enable;
};
};
i2c6_pins: i2c6-pins {
pins {
pinmux = <PINMUX_GPIO25__FUNC_SDA6>,
<PINMUX_GPIO26__FUNC_SCL6>;
bias-pull-up;
};
};
mmc0_default_pins: mmc0-default-pins {
pins-clk {
pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
drive-strength = <MTK_DRIVE_6mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
pins-cmd-dat {
pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
<PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
<PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
<PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
<PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
<PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
<PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
<PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
<PINMUX_GPIO121__FUNC_MSDC0_CMD>;
input-enable;
drive-strength = <MTK_DRIVE_6mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins-rst {
pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
drive-strength = <MTK_DRIVE_6mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
mmc0_uhs_pins: mmc0-uhs-pins {
pins-clk {
pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
pins-cmd-dat {
pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
<PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
<PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
<PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
<PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
<PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
<PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
<PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
<PINMUX_GPIO121__FUNC_MSDC0_CMD>;
input-enable;
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins-ds {
pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>;
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
pins-rst {
pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
mmc1_default_pins: mmc1-default-pins {
pins-clk {
pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
pins-cmd-dat {
pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
<PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
<PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
<PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
<PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
input-enable;
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins-insert {
pinmux = <PINMUX_GPIO129__FUNC_GPIO129>;
bias-pull-up;
};
};
mmc1_uhs_pins: mmc1-uhs-pins {
pins-clk {
pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
pins-cmd-dat {
pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
<PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
<PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
<PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
<PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
input-enable;
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
uart0_pins: uart0-pins {
pins {
pinmux = <PINMUX_GPIO98__FUNC_UTXD0>,
<PINMUX_GPIO99__FUNC_URXD0>;
};
};
uart1_pins: uart1-pins {
pins {
pinmux = <PINMUX_GPIO102__FUNC_UTXD1>,
<PINMUX_GPIO103__FUNC_URXD1>;
};
};
};
&pmic {
interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
&u3phy0 {
status = "okay";
};
&u3phy1 {
status = "okay";
};
&u3phy2 {
status = "okay";
};
&u3phy3 {
status = "okay";
};
&xhci0 {
vusb33-supply = <&mt6359_vusb_ldo_reg>;
vbus-supply = <&otg_vbus_regulator>;
status = "okay";
};
&xhci1 {
vusb33-supply = <&mt6359_vusb_ldo_reg>;
status = "okay";
};
&xhci2 {
vusb33-supply = <&mt6359_vusb_ldo_reg>;
status = "okay";
};
&xhci3 {
vusb33-supply = <&mt6359_vusb_ldo_reg>;
status = "okay";
};
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