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![Richard Cochran](/assets/img/avatar_default.png)
When performing a suspend operation, the kernel brings all of the non-boot CPUs offline, calling the hot plug notifiers with the flag, CPU_TASKS_FROZEN, set in the action code. Similarly, during resume, the CPUs are brought back online, but again the notifiers have the FROZEN flag set. While some very few drivers really need to treat suspend/resume specially, this driver unintentionally ignores the notifications. This patch changes the driver to disable the watchdog interrupt whenever the CPU goes offline, and to enable it whenever the CPU goes back online. As a result, the suspended state is no longer a special case that leaves the watchdog active. Signed-off-by: Richard Cochran <rcochran@linutronix.de> Cc: linux-watchdog@vger.kernel.org Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
656 lines
17 KiB
C
656 lines
17 KiB
C
/*
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* Octeon Watchdog driver
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*
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* Copyright (C) 2007, 2008, 2009, 2010 Cavium Networks
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*
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* Converted to use WATCHDOG_CORE by Aaro Koskinen <aaro.koskinen@iki.fi>.
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*
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* Some parts derived from wdt.c
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*
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* (c) Copyright 1996-1997 Alan Cox <alan@lxorguk.ukuu.org.uk>,
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* All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* Neither Alan Cox nor CymruNet Ltd. admit liability nor provide
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* warranty for any of this software. This material is provided
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* "AS-IS" and at no charge.
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*
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* (c) Copyright 1995 Alan Cox <alan@lxorguk.ukuu.org.uk>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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*
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* The OCTEON watchdog has a maximum timeout of 2^32 * io_clock.
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* For most systems this is less than 10 seconds, so to allow for
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* software to request longer watchdog heartbeats, we maintain software
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* counters to count multiples of the base rate. If the system locks
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* up in such a manner that we can not run the software counters, the
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* only result is a watchdog reset sooner than was requested. But
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* that is OK, because in this case userspace would likely not be able
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* to do anything anyhow.
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*
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* The hardware watchdog interval we call the period. The OCTEON
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* watchdog goes through several stages, after the first period an
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* irq is asserted, then if it is not reset, after the next period NMI
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* is asserted, then after an additional period a chip wide soft reset.
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* So for the software counters, we reset watchdog after each period
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* and decrement the counter. But for the last two periods we need to
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* let the watchdog progress to the NMI stage so we disable the irq
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* and let it proceed. Once in the NMI, we print the register state
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* to the serial port and then wait for the reset.
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*
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* A watchdog is maintained for each CPU in the system, that way if
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* one CPU suffers a lockup, we also get a register dump and reset.
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* The userspace ping resets the watchdog on all CPUs.
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*
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* Before userspace opens the watchdog device, we still run the
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* watchdogs to catch any lockups that may be kernel related.
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*
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/miscdevice.h>
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#include <linux/interrupt.h>
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#include <linux/watchdog.h>
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#include <linux/cpumask.h>
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#include <linux/bitops.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/string.h>
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#include <linux/delay.h>
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#include <linux/cpu.h>
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#include <linux/smp.h>
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#include <linux/fs.h>
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#include <linux/irq.h>
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#include <asm/mipsregs.h>
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#include <asm/uasm.h>
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#include <asm/octeon/octeon.h>
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/* The count needed to achieve timeout_sec. */
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static unsigned int timeout_cnt;
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/* The maximum period supported. */
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static unsigned int max_timeout_sec;
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/* The current period. */
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static unsigned int timeout_sec;
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/* Set to non-zero when userspace countdown mode active */
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static int do_coundown;
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static unsigned int countdown_reset;
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static unsigned int per_cpu_countdown[NR_CPUS];
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static cpumask_t irq_enabled_cpus;
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#define WD_TIMO 60 /* Default heartbeat = 60 seconds */
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static int heartbeat = WD_TIMO;
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module_param(heartbeat, int, S_IRUGO);
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MODULE_PARM_DESC(heartbeat,
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"Watchdog heartbeat in seconds. (0 < heartbeat, default="
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__MODULE_STRING(WD_TIMO) ")");
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static bool nowayout = WATCHDOG_NOWAYOUT;
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module_param(nowayout, bool, S_IRUGO);
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MODULE_PARM_DESC(nowayout,
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"Watchdog cannot be stopped once started (default="
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__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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static u32 nmi_stage1_insns[64] __initdata;
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/* We need one branch and therefore one relocation per target label. */
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static struct uasm_label labels[5] __initdata;
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static struct uasm_reloc relocs[5] __initdata;
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enum lable_id {
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label_enter_bootloader = 1
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};
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/* Some CP0 registers */
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#define K0 26
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#define C0_CVMMEMCTL 11, 7
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#define C0_STATUS 12, 0
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#define C0_EBASE 15, 1
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#define C0_DESAVE 31, 0
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void octeon_wdt_nmi_stage2(void);
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static void __init octeon_wdt_build_stage1(void)
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{
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int i;
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int len;
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u32 *p = nmi_stage1_insns;
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#ifdef CONFIG_HOTPLUG_CPU
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struct uasm_label *l = labels;
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struct uasm_reloc *r = relocs;
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#endif
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/*
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* For the next few instructions running the debugger may
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* cause corruption of k0 in the saved registers. Since we're
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* about to crash, nobody probably cares.
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*
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* Save K0 into the debug scratch register
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*/
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uasm_i_dmtc0(&p, K0, C0_DESAVE);
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uasm_i_mfc0(&p, K0, C0_STATUS);
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#ifdef CONFIG_HOTPLUG_CPU
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if (octeon_bootloader_entry_addr)
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uasm_il_bbit0(&p, &r, K0, ilog2(ST0_NMI),
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label_enter_bootloader);
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#endif
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/* Force 64-bit addressing enabled */
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uasm_i_ori(&p, K0, K0, ST0_UX | ST0_SX | ST0_KX);
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uasm_i_mtc0(&p, K0, C0_STATUS);
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#ifdef CONFIG_HOTPLUG_CPU
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if (octeon_bootloader_entry_addr) {
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uasm_i_mfc0(&p, K0, C0_EBASE);
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/* Coreid number in K0 */
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uasm_i_andi(&p, K0, K0, 0xf);
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/* 8 * coreid in bits 16-31 */
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uasm_i_dsll_safe(&p, K0, K0, 3 + 16);
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uasm_i_ori(&p, K0, K0, 0x8001);
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uasm_i_dsll_safe(&p, K0, K0, 16);
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uasm_i_ori(&p, K0, K0, 0x0700);
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uasm_i_drotr_safe(&p, K0, K0, 32);
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/*
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* Should result in: 0x8001,0700,0000,8*coreid which is
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* CVMX_CIU_WDOGX(coreid) - 0x0500
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*
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* Now ld K0, CVMX_CIU_WDOGX(coreid)
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*/
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uasm_i_ld(&p, K0, 0x500, K0);
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/*
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* If bit one set handle the NMI as a watchdog event.
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* otherwise transfer control to bootloader.
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*/
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uasm_il_bbit0(&p, &r, K0, 1, label_enter_bootloader);
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uasm_i_nop(&p);
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}
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#endif
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/* Clear Dcache so cvmseg works right. */
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uasm_i_cache(&p, 1, 0, 0);
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/* Use K0 to do a read/modify/write of CVMMEMCTL */
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uasm_i_dmfc0(&p, K0, C0_CVMMEMCTL);
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/* Clear out the size of CVMSEG */
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uasm_i_dins(&p, K0, 0, 0, 6);
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/* Set CVMSEG to its largest value */
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uasm_i_ori(&p, K0, K0, 0x1c0 | 54);
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/* Store the CVMMEMCTL value */
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uasm_i_dmtc0(&p, K0, C0_CVMMEMCTL);
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/* Load the address of the second stage handler */
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UASM_i_LA(&p, K0, (long)octeon_wdt_nmi_stage2);
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uasm_i_jr(&p, K0);
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uasm_i_dmfc0(&p, K0, C0_DESAVE);
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#ifdef CONFIG_HOTPLUG_CPU
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if (octeon_bootloader_entry_addr) {
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uasm_build_label(&l, p, label_enter_bootloader);
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/* Jump to the bootloader and restore K0 */
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UASM_i_LA(&p, K0, (long)octeon_bootloader_entry_addr);
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uasm_i_jr(&p, K0);
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uasm_i_dmfc0(&p, K0, C0_DESAVE);
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}
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#endif
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uasm_resolve_relocs(relocs, labels);
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len = (int)(p - nmi_stage1_insns);
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pr_debug("Synthesized NMI stage 1 handler (%d instructions)\n", len);
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pr_debug("\t.set push\n");
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pr_debug("\t.set noreorder\n");
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for (i = 0; i < len; i++)
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pr_debug("\t.word 0x%08x\n", nmi_stage1_insns[i]);
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pr_debug("\t.set pop\n");
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if (len > 32)
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panic("NMI stage 1 handler exceeds 32 instructions, was %d\n",
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len);
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}
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static int cpu2core(int cpu)
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{
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#ifdef CONFIG_SMP
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return cpu_logical_map(cpu);
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#else
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return cvmx_get_core_num();
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#endif
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}
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static int core2cpu(int coreid)
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{
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#ifdef CONFIG_SMP
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return cpu_number_map(coreid);
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#else
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return 0;
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#endif
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}
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/**
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* Poke the watchdog when an interrupt is received
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*
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* @cpl:
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* @dev_id:
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*
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* Returns
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*/
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static irqreturn_t octeon_wdt_poke_irq(int cpl, void *dev_id)
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{
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unsigned int core = cvmx_get_core_num();
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int cpu = core2cpu(core);
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if (do_coundown) {
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if (per_cpu_countdown[cpu] > 0) {
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/* We're alive, poke the watchdog */
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cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1);
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per_cpu_countdown[cpu]--;
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} else {
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/* Bad news, you are about to reboot. */
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disable_irq_nosync(cpl);
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cpumask_clear_cpu(cpu, &irq_enabled_cpus);
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}
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} else {
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/* Not open, just ping away... */
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cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1);
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}
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return IRQ_HANDLED;
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}
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/* From setup.c */
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extern int prom_putchar(char c);
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/**
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* Write a string to the uart
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*
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* @str: String to write
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*/
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static void octeon_wdt_write_string(const char *str)
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{
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/* Just loop writing one byte at a time */
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while (*str)
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prom_putchar(*str++);
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}
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/**
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* Write a hex number out of the uart
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*
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* @value: Number to display
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* @digits: Number of digits to print (1 to 16)
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*/
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static void octeon_wdt_write_hex(u64 value, int digits)
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{
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int d;
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int v;
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for (d = 0; d < digits; d++) {
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v = (value >> ((digits - d - 1) * 4)) & 0xf;
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if (v >= 10)
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prom_putchar('a' + v - 10);
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else
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prom_putchar('0' + v);
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}
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}
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static const char reg_name[][3] = {
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"$0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
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"a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
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"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
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"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
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};
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/**
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* NMI stage 3 handler. NMIs are handled in the following manner:
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* 1) The first NMI handler enables CVMSEG and transfers from
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* the bootbus region into normal memory. It is careful to not
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* destroy any registers.
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* 2) The second stage handler uses CVMSEG to save the registers
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* and create a stack for C code. It then calls the third level
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* handler with one argument, a pointer to the register values.
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* 3) The third, and final, level handler is the following C
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* function that prints out some useful infomration.
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*
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* @reg: Pointer to register state before the NMI
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*/
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void octeon_wdt_nmi_stage3(u64 reg[32])
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{
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u64 i;
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unsigned int coreid = cvmx_get_core_num();
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/*
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* Save status and cause early to get them before any changes
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* might happen.
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*/
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u64 cp0_cause = read_c0_cause();
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u64 cp0_status = read_c0_status();
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u64 cp0_error_epc = read_c0_errorepc();
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u64 cp0_epc = read_c0_epc();
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/* Delay so output from all cores output is not jumbled together. */
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__delay(100000000ull * coreid);
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octeon_wdt_write_string("\r\n*** NMI Watchdog interrupt on Core 0x");
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octeon_wdt_write_hex(coreid, 1);
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octeon_wdt_write_string(" ***\r\n");
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for (i = 0; i < 32; i++) {
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octeon_wdt_write_string("\t");
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octeon_wdt_write_string(reg_name[i]);
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octeon_wdt_write_string("\t0x");
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octeon_wdt_write_hex(reg[i], 16);
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if (i & 1)
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octeon_wdt_write_string("\r\n");
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}
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octeon_wdt_write_string("\terr_epc\t0x");
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octeon_wdt_write_hex(cp0_error_epc, 16);
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octeon_wdt_write_string("\tepc\t0x");
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octeon_wdt_write_hex(cp0_epc, 16);
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octeon_wdt_write_string("\r\n");
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octeon_wdt_write_string("\tstatus\t0x");
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octeon_wdt_write_hex(cp0_status, 16);
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octeon_wdt_write_string("\tcause\t0x");
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octeon_wdt_write_hex(cp0_cause, 16);
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octeon_wdt_write_string("\r\n");
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octeon_wdt_write_string("\tsum0\t0x");
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octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_SUM0(coreid * 2)), 16);
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octeon_wdt_write_string("\ten0\t0x");
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octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)), 16);
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octeon_wdt_write_string("\r\n");
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octeon_wdt_write_string("*** Chip soft reset soon ***\r\n");
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}
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static void octeon_wdt_disable_interrupt(int cpu)
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{
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unsigned int core;
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unsigned int irq;
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union cvmx_ciu_wdogx ciu_wdog;
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core = cpu2core(cpu);
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irq = OCTEON_IRQ_WDOG0 + core;
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/* Poke the watchdog to clear out its state */
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cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1);
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/* Disable the hardware. */
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ciu_wdog.u64 = 0;
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cvmx_write_csr(CVMX_CIU_WDOGX(core), ciu_wdog.u64);
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free_irq(irq, octeon_wdt_poke_irq);
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}
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static void octeon_wdt_setup_interrupt(int cpu)
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{
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unsigned int core;
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unsigned int irq;
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union cvmx_ciu_wdogx ciu_wdog;
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core = cpu2core(cpu);
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/* Disable it before doing anything with the interrupts. */
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ciu_wdog.u64 = 0;
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cvmx_write_csr(CVMX_CIU_WDOGX(core), ciu_wdog.u64);
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per_cpu_countdown[cpu] = countdown_reset;
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irq = OCTEON_IRQ_WDOG0 + core;
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if (request_irq(irq, octeon_wdt_poke_irq,
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IRQF_NO_THREAD, "octeon_wdt", octeon_wdt_poke_irq))
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panic("octeon_wdt: Couldn't obtain irq %d", irq);
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cpumask_set_cpu(cpu, &irq_enabled_cpus);
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/* Poke the watchdog to clear out its state */
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cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1);
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/* Finally enable the watchdog now that all handlers are installed */
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ciu_wdog.u64 = 0;
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ciu_wdog.s.len = timeout_cnt;
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ciu_wdog.s.mode = 3; /* 3 = Interrupt + NMI + Soft-Reset */
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cvmx_write_csr(CVMX_CIU_WDOGX(core), ciu_wdog.u64);
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}
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static int octeon_wdt_cpu_callback(struct notifier_block *nfb,
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unsigned long action, void *hcpu)
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{
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unsigned int cpu = (unsigned long)hcpu;
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switch (action & ~CPU_TASKS_FROZEN) {
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case CPU_DOWN_PREPARE:
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octeon_wdt_disable_interrupt(cpu);
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break;
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case CPU_ONLINE:
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case CPU_DOWN_FAILED:
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octeon_wdt_setup_interrupt(cpu);
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break;
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default:
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break;
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}
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return NOTIFY_OK;
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}
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static int octeon_wdt_ping(struct watchdog_device __always_unused *wdog)
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{
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int cpu;
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int coreid;
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for_each_online_cpu(cpu) {
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coreid = cpu2core(cpu);
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cvmx_write_csr(CVMX_CIU_PP_POKEX(coreid), 1);
|
|
per_cpu_countdown[cpu] = countdown_reset;
|
|
if ((countdown_reset || !do_coundown) &&
|
|
!cpumask_test_cpu(cpu, &irq_enabled_cpus)) {
|
|
/* We have to enable the irq */
|
|
int irq = OCTEON_IRQ_WDOG0 + coreid;
|
|
|
|
enable_irq(irq);
|
|
cpumask_set_cpu(cpu, &irq_enabled_cpus);
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void octeon_wdt_calc_parameters(int t)
|
|
{
|
|
unsigned int periods;
|
|
|
|
timeout_sec = max_timeout_sec;
|
|
|
|
|
|
/*
|
|
* Find the largest interrupt period, that can evenly divide
|
|
* the requested heartbeat time.
|
|
*/
|
|
while ((t % timeout_sec) != 0)
|
|
timeout_sec--;
|
|
|
|
periods = t / timeout_sec;
|
|
|
|
/*
|
|
* The last two periods are after the irq is disabled, and
|
|
* then to the nmi, so we subtract them off.
|
|
*/
|
|
|
|
countdown_reset = periods > 2 ? periods - 2 : 0;
|
|
heartbeat = t;
|
|
timeout_cnt = ((octeon_get_io_clock_rate() >> 8) * timeout_sec) >> 8;
|
|
}
|
|
|
|
static int octeon_wdt_set_timeout(struct watchdog_device *wdog,
|
|
unsigned int t)
|
|
{
|
|
int cpu;
|
|
int coreid;
|
|
union cvmx_ciu_wdogx ciu_wdog;
|
|
|
|
if (t <= 0)
|
|
return -1;
|
|
|
|
octeon_wdt_calc_parameters(t);
|
|
|
|
for_each_online_cpu(cpu) {
|
|
coreid = cpu2core(cpu);
|
|
cvmx_write_csr(CVMX_CIU_PP_POKEX(coreid), 1);
|
|
ciu_wdog.u64 = 0;
|
|
ciu_wdog.s.len = timeout_cnt;
|
|
ciu_wdog.s.mode = 3; /* 3 = Interrupt + NMI + Soft-Reset */
|
|
cvmx_write_csr(CVMX_CIU_WDOGX(coreid), ciu_wdog.u64);
|
|
cvmx_write_csr(CVMX_CIU_PP_POKEX(coreid), 1);
|
|
}
|
|
octeon_wdt_ping(wdog); /* Get the irqs back on. */
|
|
return 0;
|
|
}
|
|
|
|
static int octeon_wdt_start(struct watchdog_device *wdog)
|
|
{
|
|
octeon_wdt_ping(wdog);
|
|
do_coundown = 1;
|
|
return 0;
|
|
}
|
|
|
|
static int octeon_wdt_stop(struct watchdog_device *wdog)
|
|
{
|
|
do_coundown = 0;
|
|
octeon_wdt_ping(wdog);
|
|
return 0;
|
|
}
|
|
|
|
static struct notifier_block octeon_wdt_cpu_notifier = {
|
|
.notifier_call = octeon_wdt_cpu_callback,
|
|
};
|
|
|
|
static const struct watchdog_info octeon_wdt_info = {
|
|
.options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
|
|
.identity = "OCTEON",
|
|
};
|
|
|
|
static const struct watchdog_ops octeon_wdt_ops = {
|
|
.owner = THIS_MODULE,
|
|
.start = octeon_wdt_start,
|
|
.stop = octeon_wdt_stop,
|
|
.ping = octeon_wdt_ping,
|
|
.set_timeout = octeon_wdt_set_timeout,
|
|
};
|
|
|
|
static struct watchdog_device octeon_wdt = {
|
|
.info = &octeon_wdt_info,
|
|
.ops = &octeon_wdt_ops,
|
|
};
|
|
|
|
/**
|
|
* Module/ driver initialization.
|
|
*
|
|
* Returns Zero on success
|
|
*/
|
|
static int __init octeon_wdt_init(void)
|
|
{
|
|
int i;
|
|
int ret;
|
|
int cpu;
|
|
u64 *ptr;
|
|
|
|
/*
|
|
* Watchdog time expiration length = The 16 bits of LEN
|
|
* represent the most significant bits of a 24 bit decrementer
|
|
* that decrements every 256 cycles.
|
|
*
|
|
* Try for a timeout of 5 sec, if that fails a smaller number
|
|
* of even seconds,
|
|
*/
|
|
max_timeout_sec = 6;
|
|
do {
|
|
max_timeout_sec--;
|
|
timeout_cnt = ((octeon_get_io_clock_rate() >> 8) *
|
|
max_timeout_sec) >> 8;
|
|
} while (timeout_cnt > 65535);
|
|
|
|
BUG_ON(timeout_cnt == 0);
|
|
|
|
octeon_wdt_calc_parameters(heartbeat);
|
|
|
|
pr_info("Initial granularity %d Sec\n", timeout_sec);
|
|
|
|
octeon_wdt.timeout = timeout_sec;
|
|
octeon_wdt.max_timeout = UINT_MAX;
|
|
|
|
watchdog_set_nowayout(&octeon_wdt, nowayout);
|
|
|
|
ret = watchdog_register_device(&octeon_wdt);
|
|
if (ret) {
|
|
pr_err("watchdog_register_device() failed: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
/* Build the NMI handler ... */
|
|
octeon_wdt_build_stage1();
|
|
|
|
/* ... and install it. */
|
|
ptr = (u64 *) nmi_stage1_insns;
|
|
for (i = 0; i < 16; i++) {
|
|
cvmx_write_csr(CVMX_MIO_BOOT_LOC_ADR, i * 8);
|
|
cvmx_write_csr(CVMX_MIO_BOOT_LOC_DAT, ptr[i]);
|
|
}
|
|
cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0x81fc0000);
|
|
|
|
cpumask_clear(&irq_enabled_cpus);
|
|
|
|
cpu_notifier_register_begin();
|
|
for_each_online_cpu(cpu)
|
|
octeon_wdt_setup_interrupt(cpu);
|
|
|
|
__register_hotcpu_notifier(&octeon_wdt_cpu_notifier);
|
|
cpu_notifier_register_done();
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* Module / driver shutdown
|
|
*/
|
|
static void __exit octeon_wdt_cleanup(void)
|
|
{
|
|
int cpu;
|
|
|
|
watchdog_unregister_device(&octeon_wdt);
|
|
|
|
cpu_notifier_register_begin();
|
|
__unregister_hotcpu_notifier(&octeon_wdt_cpu_notifier);
|
|
|
|
for_each_online_cpu(cpu) {
|
|
int core = cpu2core(cpu);
|
|
/* Disable the watchdog */
|
|
cvmx_write_csr(CVMX_CIU_WDOGX(core), 0);
|
|
/* Free the interrupt handler */
|
|
free_irq(OCTEON_IRQ_WDOG0 + core, octeon_wdt_poke_irq);
|
|
}
|
|
|
|
cpu_notifier_register_done();
|
|
|
|
/*
|
|
* Disable the boot-bus memory, the code it points to is soon
|
|
* to go missing.
|
|
*/
|
|
cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0);
|
|
}
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Cavium Networks <support@caviumnetworks.com>");
|
|
MODULE_DESCRIPTION("Cavium Networks Octeon Watchdog driver.");
|
|
module_init(octeon_wdt_init);
|
|
module_exit(octeon_wdt_cleanup);
|