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7e4b8a4fbe
Add support for the eDMA IP version 0 driver for both register maps (legacy and unroll). The legacy register mapping was the initial implementation, which consisted in having all registers belonging to channels multiplexed, which could be change anytime (which could led a race-condition) by view port register (access to only one channel available each time). This register mapping is not very effective and efficient in a multithread environment, which has led to the development of unroll registers mapping, which consists of having all channels registers accessible any time by spreading all channels registers by an offset between them. This version supports a maximum of 16 independent channels (8 write + 8 read), which can run simultaneously. Implements a scatter-gather transfer through a linked list, where the size of linked list depends on the allocated memory divided equally among all channels. Each linked list descriptor can transfer from 1 byte to 4 Gbytes and is alignmented to DWORD. Both SAR (Source Address Register) and DAR (Destination Address Register) are alignmented to byte. Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Cc: Vinod Koul <vkoul@kernel.org> Cc: Dan Williams <dan.j.williams@intel.com> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Russell King <rmk+kernel@armlinux.org.uk> Cc: Joao Pinto <jpinto@synopsys.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
28 lines
1.1 KiB
C
28 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
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* Synopsys DesignWare eDMA v0 core
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*
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* Author: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
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*/
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#ifndef _DW_EDMA_V0_CORE_H
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#define _DW_EDMA_V0_CORE_H
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#include <linux/dma/edma.h>
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/* eDMA management callbacks */
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void dw_edma_v0_core_off(struct dw_edma *chan);
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u16 dw_edma_v0_core_ch_count(struct dw_edma *chan, enum dw_edma_dir dir);
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enum dma_status dw_edma_v0_core_ch_status(struct dw_edma_chan *chan);
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void dw_edma_v0_core_clear_done_int(struct dw_edma_chan *chan);
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void dw_edma_v0_core_clear_abort_int(struct dw_edma_chan *chan);
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u32 dw_edma_v0_core_status_done_int(struct dw_edma *chan, enum dw_edma_dir dir);
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u32 dw_edma_v0_core_status_abort_int(struct dw_edma *chan, enum dw_edma_dir dir);
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void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first);
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int dw_edma_v0_core_device_config(struct dw_edma_chan *chan);
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/* eDMA debug fs callbacks */
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void dw_edma_v0_core_debugfs_on(struct dw_edma_chip *chip);
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void dw_edma_v0_core_debugfs_off(void);
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#endif /* _DW_EDMA_V0_CORE_H */
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