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fd9c55c0ac
R-Car H3 ES1.* was only available to an internal development group and needed a lot of quirks and workarounds. These become a maintenance burden now, so our development group decided to remove upstream support and disable booting for this SoC. Public users only have ES2 onwards. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230307105645.5285-5-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
38 lines
1.1 KiB
C
38 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2016 Glider bvba
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*/
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#ifndef __DT_BINDINGS_POWER_R8A7795_SYSC_H__
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#define __DT_BINDINGS_POWER_R8A7795_SYSC_H__
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/*
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* These power domain indices match the numbers of the interrupt bits
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* representing the power areas in the various Interrupt Registers
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* (e.g. SYSCISR, Interrupt Status Register)
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*/
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#define R8A7795_PD_CA57_CPU0 0
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#define R8A7795_PD_CA57_CPU1 1
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#define R8A7795_PD_CA57_CPU2 2
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#define R8A7795_PD_CA57_CPU3 3
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#define R8A7795_PD_CA53_CPU0 5
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#define R8A7795_PD_CA53_CPU1 6
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#define R8A7795_PD_CA53_CPU2 7
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#define R8A7795_PD_CA53_CPU3 8
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#define R8A7795_PD_A3VP 9
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#define R8A7795_PD_CA57_SCU 12
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#define R8A7795_PD_CR7 13
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#define R8A7795_PD_A3VC 14
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#define R8A7795_PD_3DG_A 17
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#define R8A7795_PD_3DG_B 18
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#define R8A7795_PD_3DG_C 19
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#define R8A7795_PD_3DG_D 20
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#define R8A7795_PD_CA53_SCU 21
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#define R8A7795_PD_3DG_E 22
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#define R8A7795_PD_A3IR 24
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#define R8A7795_PD_A2VC1 26
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/* Always-on power area */
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#define R8A7795_PD_ALWAYS_ON 32
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#endif /* __DT_BINDINGS_POWER_R8A7795_SYSC_H__ */
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