| .. |
|
clk-audio-sync.c
|
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201
|
2019-05-30 11:29:52 -07:00 |
|
clk-bpmp.c
|
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500
|
2019-06-19 17:09:55 +02:00 |
|
clk-dfll.c
|
clk: tegra: Do not return 0 on failure
|
2020-12-30 11:54:26 +01:00 |
|
clk-dfll.h
|
clk: tegra: clk-dfll: Add suspend and resume support
|
2019-11-11 14:53:03 +01:00 |
|
clk-divider.c
|
clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation
|
2020-01-10 15:50:05 +01:00 |
|
clk-id.h
|
clk: tegra: Fix duplicated SE clock entry
|
2020-12-30 11:53:49 +01:00 |
|
clk-periph-fixed.c
|
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201
|
2019-05-30 11:29:52 -07:00 |
|
clk-periph-gate.c
|
clk: tegra: Fix refcounting of gate clocks
|
2021-07-19 09:44:43 +02:00 |
|
clk-periph.c
|
clk: tegra: Fix refcounting of gate clocks
|
2021-07-19 09:44:43 +02:00 |
|
clk-pll-out.c
|
clk: tegra: pllout: Save and restore pllout context
|
2019-11-11 14:53:02 +01:00 |
|
clk-pll.c
|
clk: tegra: Ensure that PLLU configuration is applied properly
|
2021-07-19 09:44:43 +02:00 |
|
clk-sdmmc-mux.c
|
clk: tegra: Implement disable_unused() of tegra_clk_sdmmc_mux_ops
|
2021-08-12 13:22:04 +02:00 |
|
clk-super.c
|
clk: tegra: clk-super: Add restore-context support
|
2019-11-11 14:53:03 +01:00 |
|
clk-tegra-audio.c
|
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201
|
2019-05-30 11:29:52 -07:00 |
|
clk-tegra-fixed.c
|
clk: tegra: Remove CLK_M_DIV fixed clocks
|
2020-03-12 11:33:32 +01:00 |
|
clk-tegra-periph.c
|
clk: tegra: Fix duplicated SE clock entry
|
2020-12-30 11:53:49 +01:00 |
|
clk-tegra-super-cclk.c
|
clk: tegra: cclk: Add helpers for handling PLLX rate changes
|
2020-05-12 22:48:43 +02:00 |
|
clk-tegra-super-gen4.c
|
clk: tegra: clk-super: Fix to enable PLLP branches to CPU
|
2019-11-11 14:53:03 +01:00 |
|
clk-tegra20-emc.c
|
clk: tegra: Add Tegra20/30 EMC clock implementation
|
2019-11-11 14:01:22 +01:00 |
|
clk-tegra20.c
|
clk: tegra20: Use custom CCLK implementation
|
2020-05-12 22:48:43 +02:00 |
|
clk-tegra30.c
|
clk: tegra30: Use 300MHz for video decoder by default
|
2021-07-14 16:56:19 +02:00 |
|
clk-tegra114.c
|
clk: tegra: Remove audio clocks configuration from clock driver
|
2020-03-12 12:10:49 +01:00 |
|
clk-tegra124-dfll-fcpu.c
|
clk: tegra: clk-dfll: Add suspend and resume support
|
2019-11-11 14:53:03 +01:00 |
|
clk-tegra124-emc.c
|
clk: tegra: Rename Tegra124 EMC clock source file
|
2020-05-12 22:48:41 +02:00 |
|
clk-tegra124.c
|
clk: tegra: Fix initial rate for pll_a on Tegra124
|
2020-05-12 16:26:18 -07:00 |
|
clk-tegra210-emc.c
|
This pull request contains zero diff to the core framework. It is a collection
|
2020-10-22 12:53:28 -07:00 |
|
clk-tegra210.c
|
clk: tegra: Add Tegra210 CSI TPG clock gate
|
2020-05-12 22:48:43 +02:00 |
|
clk-utils.c
|
clk: tegra: Refactor fractional divider calculation
|
2018-07-25 13:43:34 -07:00 |
|
clk.c
|
clk: tegra: Fix double-free in tegra_clk_init()
|
2019-12-24 00:01:06 -08:00 |
|
clk.h
|
clk: tegra: cclk: Add helpers for handling PLLX rate changes
|
2020-05-12 22:48:43 +02:00 |
|
cvb.c
|
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174
|
2019-05-30 11:26:41 -07:00 |
|
cvb.h
|
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174
|
2019-05-30 11:26:41 -07:00 |
|
Kconfig
|
clk: tegra: Rename Tegra124 EMC clock source file
|
2020-05-12 22:48:41 +02:00 |
|
Makefile
|
clk: tegra: Add custom CCLK implementation
|
2020-05-12 22:48:42 +02:00 |
84656b4c27