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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 228 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
122 lines
2.7 KiB
C
122 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef __LINUX_CLK_TEGRA_H_
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#define __LINUX_CLK_TEGRA_H_
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#include <linux/types.h>
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#include <linux/bug.h>
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/*
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* Tegra CPU clock and reset control ops
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*
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* wait_for_reset:
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* keep waiting until the CPU in reset state
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* put_in_reset:
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* put the CPU in reset state
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* out_of_reset:
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* release the CPU from reset state
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* enable_clock:
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* CPU clock un-gate
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* disable_clock:
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* CPU clock gate
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* rail_off_ready:
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* CPU is ready for rail off
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* suspend:
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* save the clock settings when CPU go into low-power state
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* resume:
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* restore the clock settings when CPU exit low-power state
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*/
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struct tegra_cpu_car_ops {
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void (*wait_for_reset)(u32 cpu);
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void (*put_in_reset)(u32 cpu);
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void (*out_of_reset)(u32 cpu);
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void (*enable_clock)(u32 cpu);
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void (*disable_clock)(u32 cpu);
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#ifdef CONFIG_PM_SLEEP
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bool (*rail_off_ready)(void);
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void (*suspend)(void);
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void (*resume)(void);
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#endif
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};
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extern struct tegra_cpu_car_ops *tegra_cpu_car_ops;
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static inline void tegra_wait_cpu_in_reset(u32 cpu)
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{
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if (WARN_ON(!tegra_cpu_car_ops->wait_for_reset))
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return;
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tegra_cpu_car_ops->wait_for_reset(cpu);
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}
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static inline void tegra_put_cpu_in_reset(u32 cpu)
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{
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if (WARN_ON(!tegra_cpu_car_ops->put_in_reset))
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return;
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tegra_cpu_car_ops->put_in_reset(cpu);
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}
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static inline void tegra_cpu_out_of_reset(u32 cpu)
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{
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if (WARN_ON(!tegra_cpu_car_ops->out_of_reset))
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return;
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tegra_cpu_car_ops->out_of_reset(cpu);
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}
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static inline void tegra_enable_cpu_clock(u32 cpu)
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{
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if (WARN_ON(!tegra_cpu_car_ops->enable_clock))
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return;
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tegra_cpu_car_ops->enable_clock(cpu);
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}
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static inline void tegra_disable_cpu_clock(u32 cpu)
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{
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if (WARN_ON(!tegra_cpu_car_ops->disable_clock))
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return;
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tegra_cpu_car_ops->disable_clock(cpu);
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}
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#ifdef CONFIG_PM_SLEEP
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static inline bool tegra_cpu_rail_off_ready(void)
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{
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if (WARN_ON(!tegra_cpu_car_ops->rail_off_ready))
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return false;
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return tegra_cpu_car_ops->rail_off_ready();
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}
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static inline void tegra_cpu_clock_suspend(void)
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{
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if (WARN_ON(!tegra_cpu_car_ops->suspend))
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return;
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tegra_cpu_car_ops->suspend();
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}
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static inline void tegra_cpu_clock_resume(void)
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{
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if (WARN_ON(!tegra_cpu_car_ops->resume))
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return;
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tegra_cpu_car_ops->resume();
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}
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#endif
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extern void tegra210_xusb_pll_hw_control_enable(void);
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extern void tegra210_xusb_pll_hw_sequence_start(void);
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extern void tegra210_sata_pll_hw_control_enable(void);
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extern void tegra210_sata_pll_hw_sequence_start(void);
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extern void tegra210_set_sata_pll_seq_sw(bool state);
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extern void tegra210_put_utmipll_in_iddq(void);
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extern void tegra210_put_utmipll_out_iddq(void);
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extern int tegra210_clk_handle_mbist_war(unsigned int id);
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#endif /* __LINUX_CLK_TEGRA_H_ */
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