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6058f11870
GCE hardware stored event information in own internal sysram,
if the initial value in those sysram is not zero value
it will cause a situation that gce can wait the event immediately
after client ask gce to wait event but not really trigger the
corresponding hardware.
In order to make sure that the wait event function is
exactly correct, we need to clear the sysram value in
cmdq initial flow.
Fixes: 623a6143a8 ("mailbox: mediatek: Add Mediatek CMDQ driver")
Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
80 lines
1.7 KiB
C
80 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2018 MediaTek Inc.
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*
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*/
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#ifndef __MTK_CMDQ_MAILBOX_H__
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#define __MTK_CMDQ_MAILBOX_H__
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#define CMDQ_INST_SIZE 8 /* instruction is 64-bit */
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#define CMDQ_SUBSYS_SHIFT 16
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#define CMDQ_OP_CODE_SHIFT 24
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#define CMDQ_JUMP_PASS CMDQ_INST_SIZE
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#define CMDQ_WFE_UPDATE BIT(31)
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#define CMDQ_WFE_WAIT BIT(15)
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#define CMDQ_WFE_WAIT_VALUE 0x1
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/** cmdq event maximum */
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#define CMDQ_MAX_EVENT 0x3ff
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/*
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* CMDQ_CODE_MASK:
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* set write mask
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* format: op mask
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* CMDQ_CODE_WRITE:
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* write value into target register
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* format: op subsys address value
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* CMDQ_CODE_JUMP:
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* jump by offset
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* format: op offset
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* CMDQ_CODE_WFE:
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* wait for event and clear
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* it is just clear if no wait
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* format: [wait] op event update:1 to_wait:1 wait:1
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* [clear] op event update:1 to_wait:0 wait:0
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* CMDQ_CODE_EOC:
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* end of command
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* format: op irq_flag
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*/
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enum cmdq_code {
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CMDQ_CODE_MASK = 0x02,
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CMDQ_CODE_WRITE = 0x04,
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CMDQ_CODE_JUMP = 0x10,
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CMDQ_CODE_WFE = 0x20,
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CMDQ_CODE_EOC = 0x40,
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};
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enum cmdq_cb_status {
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CMDQ_CB_NORMAL = 0,
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CMDQ_CB_ERROR
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};
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struct cmdq_cb_data {
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enum cmdq_cb_status sta;
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void *data;
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};
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typedef void (*cmdq_async_flush_cb)(struct cmdq_cb_data data);
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struct cmdq_task_cb {
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cmdq_async_flush_cb cb;
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void *data;
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};
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struct cmdq_pkt {
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void *va_base;
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dma_addr_t pa_base;
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size_t cmd_buf_size; /* command occupied size */
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size_t buf_size; /* real buffer size */
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struct cmdq_task_cb cb;
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struct cmdq_task_cb async_cb;
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void *cl;
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};
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#endif /* __MTK_CMDQ_MAILBOX_H__ */
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