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![Linus Torvalds](/assets/img/avatar_default.png)
This cycle mainly saw lots of bug fixes and clean up code across the core code and several drivers, few new functional changes were made. - Many cleanup and bug fixes for hns - Various small bug fixes and cleanups in hfi1, mlx5, usnic, qed, bnxt_re, efa - Share the query_port code between all the iWarp drivers - General rework and cleanup of the ODP MR umem code to fit better with the mmu notifier get/put scheme - Support rdma netlink in non init_net name spaces - mlx5 support for XRC devx and DC ODP -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEfB7FMLh+8QxL+6i3OG33FX4gmxoFAl2A1ugACgkQOG33FX4g mxp+EQ//Ug8CyyDs40SGZztItoGghuQ4TVA2pXtuZ9LkFVJRWhYPJGOadHIYXqGO KQJJpZPQ02HTZUPWBZNKmD5bwHfErm4cS73/mVmUpximnUqu/UsLRJp8SIGmBg1D W1Lz1BJX24MdV8aUnChYvdL5Hbl52q+BaE99Z0haOvW7I3YnKJC34mR8m/A5MiRf rsNIZNPHdq2U6pKLgCbOyXib8yBcJQqBb8x4WNAoB1h4MOx+ir5QLfr3ozrZs1an xXgqyiOBmtkUgCMIpXC4juPN/6gw3Y5nkk2VIWY+MAY1a7jZPbI+6LJZZ1Uk8R44 Lf2KSzabFMMYGKJYE1Znxk+JWV8iE+m+n6wWEfRM9l0b4gXXbrtKgaouFbsLcsQA CvBEQuiFSO9Kq01JPaAN1XDmhqyTarG6lHjXnW7ifNlLXnPbR1RJlprycExOhp0c axum5K2fRNW2+uZJt+zynMjk2kyjT1lnlsr1Rbgc4Pyionaiydg7zwpiac7y/bdS F7/WqdmPiff78KMi187EF5pjFqMWhthvBtTbWDuuxaxc2nrXSdiCUN+96j1amQUH yU/7AZzlnKeKEQQCR4xddsSs2eTrXiLLFRLk9GCK2eh4cUN212eHTrPLKkQf1cN+ ydYbR2pxw3B38LCCNBy+bL+u7e/Tyehs4ynATMpBuEgc5iocTwE= =zHXW -----END PGP SIGNATURE----- Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma Pull RDMA subsystem updates from Jason Gunthorpe: "This cycle mainly saw lots of bug fixes and clean up code across the core code and several drivers, few new functional changes were made. - Many cleanup and bug fixes for hns - Various small bug fixes and cleanups in hfi1, mlx5, usnic, qed, bnxt_re, efa - Share the query_port code between all the iWarp drivers - General rework and cleanup of the ODP MR umem code to fit better with the mmu notifier get/put scheme - Support rdma netlink in non init_net name spaces - mlx5 support for XRC devx and DC ODP" * tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma: (99 commits) RDMA: Fix double-free in srq creation error flow RDMA/efa: Fix incorrect error print IB/mlx5: Free mpi in mp_slave mode IB/mlx5: Use the original address for the page during free_pages RDMA/bnxt_re: Fix spelling mistake "missin_resp" -> "missing_resp" RDMA/hns: Package operations of rq inline buffer into separate functions RDMA/hns: Optimize cmd init and mode selection for hip08 IB/hfi1: Define variables as unsigned long to fix KASAN warning IB/{rdmavt, hfi1, qib}: Add a counter for credit waits IB/hfi1: Add traces for TID RDMA READ RDMA/siw: Relax from kmap_atomic() use in TX path IB/iser: Support up to 16MB data transfer in a single command RDMA/siw: Fix page address mapping in TX path RDMA: Fix goto target to release the allocated memory RDMA/usnic: Avoid overly large buffers on stack RDMA/odp: Add missing cast for 32 bit RDMA/hns: Use devm_platform_ioremap_resource() to simplify code Documentation/infiniband: update name of some functions RDMA/cma: Fix false error message RDMA/hns: Fix wrong assignment of qp_access_flags ...
1351 lines
33 KiB
C
1351 lines
33 KiB
C
/*
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* Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef MLX5_DEVICE_H
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#define MLX5_DEVICE_H
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#include <linux/types.h>
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#include <rdma/ib_verbs.h>
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#include <linux/mlx5/mlx5_ifc.h>
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#if defined(__LITTLE_ENDIAN)
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#define MLX5_SET_HOST_ENDIANNESS 0
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#elif defined(__BIG_ENDIAN)
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#define MLX5_SET_HOST_ENDIANNESS 0x80
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#else
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#error Host endianness not defined
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#endif
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/* helper macros */
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#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
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#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
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#define __mlx5_bit_off(typ, fld) (offsetof(struct mlx5_ifc_##typ##_bits, fld))
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#define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
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#define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
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#define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
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#define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf))
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#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
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#define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
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#define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
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#define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
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#define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld))
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#define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
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#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
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#define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
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#define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
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#define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
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#define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
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#define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
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#define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
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#define MLX5_ADDR_OF(typ, p, fld) ((void *)((uint8_t *)(p) + MLX5_BYTE_OFF(typ, fld)))
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/* insert a value to a struct */
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#define MLX5_SET(typ, p, fld, v) do { \
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u32 _v = v; \
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BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
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*((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
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cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
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(~__mlx5_dw_mask(typ, fld))) | (((_v) & __mlx5_mask(typ, fld)) \
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<< __mlx5_dw_bit_off(typ, fld))); \
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} while (0)
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#define MLX5_ARRAY_SET(typ, p, fld, idx, v) do { \
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BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 32); \
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MLX5_SET(typ, p, fld[idx], v); \
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} while (0)
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#define MLX5_SET_TO_ONES(typ, p, fld) do { \
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BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
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*((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
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cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
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(~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
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<< __mlx5_dw_bit_off(typ, fld))); \
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} while (0)
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#define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
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__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
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__mlx5_mask(typ, fld))
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#define MLX5_GET_PR(typ, p, fld) ({ \
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u32 ___t = MLX5_GET(typ, p, fld); \
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pr_debug(#fld " = 0x%x\n", ___t); \
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___t; \
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})
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#define __MLX5_SET64(typ, p, fld, v) do { \
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BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
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*((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
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} while (0)
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#define MLX5_SET64(typ, p, fld, v) do { \
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BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
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__MLX5_SET64(typ, p, fld, v); \
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} while (0)
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#define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \
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BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
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__MLX5_SET64(typ, p, fld[idx], v); \
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} while (0)
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#define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
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#define MLX5_GET64_PR(typ, p, fld) ({ \
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u64 ___t = MLX5_GET64(typ, p, fld); \
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pr_debug(#fld " = 0x%llx\n", ___t); \
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___t; \
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})
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#define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\
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__mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
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__mlx5_mask16(typ, fld))
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#define MLX5_SET16(typ, p, fld, v) do { \
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u16 _v = v; \
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BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \
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*((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \
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cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \
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(~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \
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<< __mlx5_16_bit_off(typ, fld))); \
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} while (0)
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/* Big endian getters */
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#define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
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__mlx5_64_off(typ, fld)))
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#define MLX5_GET_BE(type_t, typ, p, fld) ({ \
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type_t tmp; \
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switch (sizeof(tmp)) { \
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case sizeof(u8): \
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tmp = (__force type_t)MLX5_GET(typ, p, fld); \
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break; \
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case sizeof(u16): \
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tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
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break; \
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case sizeof(u32): \
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tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
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break; \
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case sizeof(u64): \
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tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
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break; \
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} \
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tmp; \
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})
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enum mlx5_inline_modes {
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MLX5_INLINE_MODE_NONE,
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MLX5_INLINE_MODE_L2,
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MLX5_INLINE_MODE_IP,
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MLX5_INLINE_MODE_TCP_UDP,
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};
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enum {
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MLX5_MAX_COMMANDS = 32,
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MLX5_CMD_DATA_BLOCK_SIZE = 512,
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MLX5_PCI_CMD_XPORT = 7,
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MLX5_MKEY_BSF_OCTO_SIZE = 4,
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MLX5_MAX_PSVS = 4,
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};
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enum {
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MLX5_EXTENDED_UD_AV = 0x80000000,
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};
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enum {
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MLX5_CQ_STATE_ARMED = 9,
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MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
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MLX5_CQ_STATE_FIRED = 0xa,
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};
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enum {
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MLX5_STAT_RATE_OFFSET = 5,
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};
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enum {
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MLX5_INLINE_SEG = 0x80000000,
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};
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enum {
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MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
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};
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enum {
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MLX5_MIN_PKEY_TABLE_SIZE = 128,
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MLX5_MAX_LOG_PKEY_TABLE = 5,
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};
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enum {
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MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
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};
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enum {
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MLX5_PFAULT_SUBTYPE_WQE = 0,
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MLX5_PFAULT_SUBTYPE_RDMA = 1,
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};
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enum wqe_page_fault_type {
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MLX5_WQE_PF_TYPE_RMP = 0,
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MLX5_WQE_PF_TYPE_REQ_SEND_OR_WRITE = 1,
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MLX5_WQE_PF_TYPE_RESP = 2,
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MLX5_WQE_PF_TYPE_REQ_READ_OR_ATOMIC = 3,
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};
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enum {
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MLX5_PERM_LOCAL_READ = 1 << 2,
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MLX5_PERM_LOCAL_WRITE = 1 << 3,
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MLX5_PERM_REMOTE_READ = 1 << 4,
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MLX5_PERM_REMOTE_WRITE = 1 << 5,
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MLX5_PERM_ATOMIC = 1 << 6,
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MLX5_PERM_UMR_EN = 1 << 7,
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};
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enum {
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MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
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MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
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MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
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MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
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MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
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};
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enum {
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MLX5_EN_RD = (u64)1,
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MLX5_EN_WR = (u64)2
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};
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enum {
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MLX5_ADAPTER_PAGE_SHIFT = 12,
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MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
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};
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enum {
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MLX5_BFREGS_PER_UAR = 4,
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MLX5_MAX_UARS = 1 << 8,
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MLX5_NON_FP_BFREGS_PER_UAR = 2,
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MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR -
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MLX5_NON_FP_BFREGS_PER_UAR,
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MLX5_MAX_BFREGS = MLX5_MAX_UARS *
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MLX5_NON_FP_BFREGS_PER_UAR,
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MLX5_UARS_IN_PAGE = PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE,
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MLX5_NON_FP_BFREGS_IN_PAGE = MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE,
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MLX5_MIN_DYN_BFREGS = 512,
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MLX5_MAX_DYN_BFREGS = 1024,
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};
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enum {
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MLX5_MKEY_MASK_LEN = 1ull << 0,
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MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
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MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
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MLX5_MKEY_MASK_PD = 1ull << 7,
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MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
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MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
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MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
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MLX5_MKEY_MASK_KEY = 1ull << 13,
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MLX5_MKEY_MASK_QPN = 1ull << 14,
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MLX5_MKEY_MASK_LR = 1ull << 17,
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MLX5_MKEY_MASK_LW = 1ull << 18,
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MLX5_MKEY_MASK_RR = 1ull << 19,
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MLX5_MKEY_MASK_RW = 1ull << 20,
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MLX5_MKEY_MASK_A = 1ull << 21,
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MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
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MLX5_MKEY_MASK_FREE = 1ull << 29,
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};
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enum {
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MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
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MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
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MLX5_UMR_CHECK_FREE = (2 << 5),
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MLX5_UMR_INLINE = (1 << 7),
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};
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#define MLX5_UMR_MTT_ALIGNMENT 0x40
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#define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
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#define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
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#define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)
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enum {
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MLX5_EVENT_QUEUE_TYPE_QP = 0,
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MLX5_EVENT_QUEUE_TYPE_RQ = 1,
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MLX5_EVENT_QUEUE_TYPE_SQ = 2,
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MLX5_EVENT_QUEUE_TYPE_DCT = 6,
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};
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/* mlx5 components can subscribe to any one of these events via
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* mlx5_eq_notifier_register API.
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*/
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enum mlx5_event {
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/* Special value to subscribe to any event */
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MLX5_EVENT_TYPE_NOTIFY_ANY = 0x0,
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/* HW events enum start: comp events are not subscribable */
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MLX5_EVENT_TYPE_COMP = 0x0,
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/* HW Async events enum start: subscribable events */
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MLX5_EVENT_TYPE_PATH_MIG = 0x01,
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MLX5_EVENT_TYPE_COMM_EST = 0x02,
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MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
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MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
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MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
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MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
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MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
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MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
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MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
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MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
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MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
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|
|
MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
|
|
MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
|
|
MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
|
|
MLX5_EVENT_TYPE_PORT_MODULE_EVENT = 0x16,
|
|
MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17,
|
|
MLX5_EVENT_TYPE_XRQ_ERROR = 0x18,
|
|
MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
|
|
MLX5_EVENT_TYPE_GENERAL_EVENT = 0x22,
|
|
MLX5_EVENT_TYPE_MONITOR_COUNTER = 0x24,
|
|
MLX5_EVENT_TYPE_PPS_EVENT = 0x25,
|
|
|
|
MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
|
|
MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
|
|
|
|
MLX5_EVENT_TYPE_CMD = 0x0a,
|
|
MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
|
|
|
|
MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
|
|
MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,
|
|
|
|
MLX5_EVENT_TYPE_ESW_FUNCTIONS_CHANGED = 0xe,
|
|
|
|
MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c,
|
|
MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d,
|
|
|
|
MLX5_EVENT_TYPE_FPGA_ERROR = 0x20,
|
|
MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21,
|
|
|
|
MLX5_EVENT_TYPE_DEVICE_TRACER = 0x26,
|
|
|
|
MLX5_EVENT_TYPE_MAX = 0x100,
|
|
};
|
|
|
|
enum {
|
|
MLX5_TRACER_SUBTYPE_OWNERSHIP_CHANGE = 0x0,
|
|
MLX5_TRACER_SUBTYPE_TRACES_AVAILABLE = 0x1,
|
|
};
|
|
|
|
enum {
|
|
MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1,
|
|
MLX5_GENERAL_SUBTYPE_PCI_POWER_CHANGE_EVENT = 0x5,
|
|
};
|
|
|
|
enum {
|
|
MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
|
|
MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
|
|
MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
|
|
MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
|
|
MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
|
|
MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
|
|
MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
|
|
};
|
|
|
|
enum {
|
|
MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
|
|
MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
|
|
MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
|
|
MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
|
|
MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
|
|
MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
|
|
MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
|
|
MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
|
|
MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
|
|
MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
|
|
MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
|
|
MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
|
|
};
|
|
|
|
enum {
|
|
MLX5_ROCE_VERSION_1 = 0,
|
|
MLX5_ROCE_VERSION_2 = 2,
|
|
};
|
|
|
|
enum {
|
|
MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
|
|
MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
|
|
};
|
|
|
|
enum {
|
|
MLX5_ROCE_L3_TYPE_IPV4 = 0,
|
|
MLX5_ROCE_L3_TYPE_IPV6 = 1,
|
|
};
|
|
|
|
enum {
|
|
MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
|
|
MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
|
|
};
|
|
|
|
enum {
|
|
MLX5_OPCODE_NOP = 0x00,
|
|
MLX5_OPCODE_SEND_INVAL = 0x01,
|
|
MLX5_OPCODE_RDMA_WRITE = 0x08,
|
|
MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
|
|
MLX5_OPCODE_SEND = 0x0a,
|
|
MLX5_OPCODE_SEND_IMM = 0x0b,
|
|
MLX5_OPCODE_LSO = 0x0e,
|
|
MLX5_OPCODE_RDMA_READ = 0x10,
|
|
MLX5_OPCODE_ATOMIC_CS = 0x11,
|
|
MLX5_OPCODE_ATOMIC_FA = 0x12,
|
|
MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
|
|
MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
|
|
MLX5_OPCODE_BIND_MW = 0x18,
|
|
MLX5_OPCODE_CONFIG_CMD = 0x1f,
|
|
MLX5_OPCODE_ENHANCED_MPSW = 0x29,
|
|
|
|
MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
|
|
MLX5_RECV_OPCODE_SEND = 0x01,
|
|
MLX5_RECV_OPCODE_SEND_IMM = 0x02,
|
|
MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
|
|
|
|
MLX5_CQE_OPCODE_ERROR = 0x1e,
|
|
MLX5_CQE_OPCODE_RESIZE = 0x16,
|
|
|
|
MLX5_OPCODE_SET_PSV = 0x20,
|
|
MLX5_OPCODE_GET_PSV = 0x21,
|
|
MLX5_OPCODE_CHECK_PSV = 0x22,
|
|
MLX5_OPCODE_DUMP = 0x23,
|
|
MLX5_OPCODE_RGET_PSV = 0x26,
|
|
MLX5_OPCODE_RCHECK_PSV = 0x27,
|
|
|
|
MLX5_OPCODE_UMR = 0x25,
|
|
|
|
};
|
|
|
|
enum {
|
|
MLX5_OPC_MOD_TLS_TIS_STATIC_PARAMS = 0x1,
|
|
};
|
|
|
|
enum {
|
|
MLX5_OPC_MOD_TLS_TIS_PROGRESS_PARAMS = 0x1,
|
|
};
|
|
|
|
enum {
|
|
MLX5_SET_PORT_RESET_QKEY = 0,
|
|
MLX5_SET_PORT_GUID0 = 16,
|
|
MLX5_SET_PORT_NODE_GUID = 17,
|
|
MLX5_SET_PORT_SYS_GUID = 18,
|
|
MLX5_SET_PORT_GID_TABLE = 19,
|
|
MLX5_SET_PORT_PKEY_TABLE = 20,
|
|
};
|
|
|
|
enum {
|
|
MLX5_BW_NO_LIMIT = 0,
|
|
MLX5_100_MBPS_UNIT = 3,
|
|
MLX5_GBPS_UNIT = 4,
|
|
};
|
|
|
|
enum {
|
|
MLX5_MAX_PAGE_SHIFT = 31
|
|
};
|
|
|
|
enum {
|
|
MLX5_CAP_OFF_CMDIF_CSUM = 46,
|
|
};
|
|
|
|
enum {
|
|
/*
|
|
* Max wqe size for rdma read is 512 bytes, so this
|
|
* limits our max_sge_rd as the wqe needs to fit:
|
|
* - ctrl segment (16 bytes)
|
|
* - rdma segment (16 bytes)
|
|
* - scatter elements (16 bytes each)
|
|
*/
|
|
MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
|
|
};
|
|
|
|
enum mlx5_odp_transport_cap_bits {
|
|
MLX5_ODP_SUPPORT_SEND = 1 << 31,
|
|
MLX5_ODP_SUPPORT_RECV = 1 << 30,
|
|
MLX5_ODP_SUPPORT_WRITE = 1 << 29,
|
|
MLX5_ODP_SUPPORT_READ = 1 << 28,
|
|
};
|
|
|
|
struct mlx5_odp_caps {
|
|
char reserved[0x10];
|
|
struct {
|
|
__be32 rc_odp_caps;
|
|
__be32 uc_odp_caps;
|
|
__be32 ud_odp_caps;
|
|
} per_transport_caps;
|
|
char reserved2[0xe4];
|
|
};
|
|
|
|
struct mlx5_cmd_layout {
|
|
u8 type;
|
|
u8 rsvd0[3];
|
|
__be32 inlen;
|
|
__be64 in_ptr;
|
|
__be32 in[4];
|
|
__be32 out[4];
|
|
__be64 out_ptr;
|
|
__be32 outlen;
|
|
u8 token;
|
|
u8 sig;
|
|
u8 rsvd1;
|
|
u8 status_own;
|
|
};
|
|
|
|
enum mlx5_fatal_assert_bit_offsets {
|
|
MLX5_RFR_OFFSET = 31,
|
|
};
|
|
|
|
struct health_buffer {
|
|
__be32 assert_var[5];
|
|
__be32 rsvd0[3];
|
|
__be32 assert_exit_ptr;
|
|
__be32 assert_callra;
|
|
__be32 rsvd1[2];
|
|
__be32 fw_ver;
|
|
__be32 hw_id;
|
|
__be32 rfr;
|
|
u8 irisc_index;
|
|
u8 synd;
|
|
__be16 ext_synd;
|
|
};
|
|
|
|
enum mlx5_initializing_bit_offsets {
|
|
MLX5_FW_RESET_SUPPORTED_OFFSET = 30,
|
|
};
|
|
|
|
enum mlx5_cmd_addr_l_sz_offset {
|
|
MLX5_NIC_IFC_OFFSET = 8,
|
|
};
|
|
|
|
struct mlx5_init_seg {
|
|
__be32 fw_rev;
|
|
__be32 cmdif_rev_fw_sub;
|
|
__be32 rsvd0[2];
|
|
__be32 cmdq_addr_h;
|
|
__be32 cmdq_addr_l_sz;
|
|
__be32 cmd_dbell;
|
|
__be32 rsvd1[120];
|
|
__be32 initializing;
|
|
struct health_buffer health;
|
|
__be32 rsvd2[880];
|
|
__be32 internal_timer_h;
|
|
__be32 internal_timer_l;
|
|
__be32 rsvd3[2];
|
|
__be32 health_counter;
|
|
__be32 rsvd4[1019];
|
|
__be64 ieee1588_clk;
|
|
__be32 ieee1588_clk_type;
|
|
__be32 clr_intx;
|
|
};
|
|
|
|
struct mlx5_eqe_comp {
|
|
__be32 reserved[6];
|
|
__be32 cqn;
|
|
};
|
|
|
|
struct mlx5_eqe_qp_srq {
|
|
__be32 reserved1[5];
|
|
u8 type;
|
|
u8 reserved2[3];
|
|
__be32 qp_srq_n;
|
|
};
|
|
|
|
struct mlx5_eqe_cq_err {
|
|
__be32 cqn;
|
|
u8 reserved1[7];
|
|
u8 syndrome;
|
|
};
|
|
|
|
struct mlx5_eqe_xrq_err {
|
|
__be32 reserved1[5];
|
|
__be32 type_xrqn;
|
|
__be32 reserved2;
|
|
};
|
|
|
|
struct mlx5_eqe_port_state {
|
|
u8 reserved0[8];
|
|
u8 port;
|
|
};
|
|
|
|
struct mlx5_eqe_gpio {
|
|
__be32 reserved0[2];
|
|
__be64 gpio_event;
|
|
};
|
|
|
|
struct mlx5_eqe_congestion {
|
|
u8 type;
|
|
u8 rsvd0;
|
|
u8 congestion_level;
|
|
};
|
|
|
|
struct mlx5_eqe_stall_vl {
|
|
u8 rsvd0[3];
|
|
u8 port_vl;
|
|
};
|
|
|
|
struct mlx5_eqe_cmd {
|
|
__be32 vector;
|
|
__be32 rsvd[6];
|
|
};
|
|
|
|
struct mlx5_eqe_page_req {
|
|
__be16 ec_function;
|
|
__be16 func_id;
|
|
__be32 num_pages;
|
|
__be32 rsvd1[5];
|
|
};
|
|
|
|
struct mlx5_eqe_page_fault {
|
|
__be32 bytes_committed;
|
|
union {
|
|
struct {
|
|
u16 reserved1;
|
|
__be16 wqe_index;
|
|
u16 reserved2;
|
|
__be16 packet_length;
|
|
__be32 token;
|
|
u8 reserved4[8];
|
|
__be32 pftype_wq;
|
|
} __packed wqe;
|
|
struct {
|
|
__be32 r_key;
|
|
u16 reserved1;
|
|
__be16 packet_length;
|
|
__be32 rdma_op_len;
|
|
__be64 rdma_va;
|
|
__be32 pftype_token;
|
|
} __packed rdma;
|
|
} __packed;
|
|
} __packed;
|
|
|
|
struct mlx5_eqe_vport_change {
|
|
u8 rsvd0[2];
|
|
__be16 vport_num;
|
|
__be32 rsvd1[6];
|
|
} __packed;
|
|
|
|
struct mlx5_eqe_port_module {
|
|
u8 reserved_at_0[1];
|
|
u8 module;
|
|
u8 reserved_at_2[1];
|
|
u8 module_status;
|
|
u8 reserved_at_4[2];
|
|
u8 error_type;
|
|
} __packed;
|
|
|
|
struct mlx5_eqe_pps {
|
|
u8 rsvd0[3];
|
|
u8 pin;
|
|
u8 rsvd1[4];
|
|
union {
|
|
struct {
|
|
__be32 time_sec;
|
|
__be32 time_nsec;
|
|
};
|
|
struct {
|
|
__be64 time_stamp;
|
|
};
|
|
};
|
|
u8 rsvd2[12];
|
|
} __packed;
|
|
|
|
struct mlx5_eqe_dct {
|
|
__be32 reserved[6];
|
|
__be32 dctn;
|
|
};
|
|
|
|
struct mlx5_eqe_temp_warning {
|
|
__be64 sensor_warning_msb;
|
|
__be64 sensor_warning_lsb;
|
|
} __packed;
|
|
|
|
union ev_data {
|
|
__be32 raw[7];
|
|
struct mlx5_eqe_cmd cmd;
|
|
struct mlx5_eqe_comp comp;
|
|
struct mlx5_eqe_qp_srq qp_srq;
|
|
struct mlx5_eqe_cq_err cq_err;
|
|
struct mlx5_eqe_port_state port;
|
|
struct mlx5_eqe_gpio gpio;
|
|
struct mlx5_eqe_congestion cong;
|
|
struct mlx5_eqe_stall_vl stall_vl;
|
|
struct mlx5_eqe_page_req req_pages;
|
|
struct mlx5_eqe_page_fault page_fault;
|
|
struct mlx5_eqe_vport_change vport_change;
|
|
struct mlx5_eqe_port_module port_module;
|
|
struct mlx5_eqe_pps pps;
|
|
struct mlx5_eqe_dct dct;
|
|
struct mlx5_eqe_temp_warning temp_warning;
|
|
struct mlx5_eqe_xrq_err xrq_err;
|
|
} __packed;
|
|
|
|
struct mlx5_eqe {
|
|
u8 rsvd0;
|
|
u8 type;
|
|
u8 rsvd1;
|
|
u8 sub_type;
|
|
__be32 rsvd2[7];
|
|
union ev_data data;
|
|
__be16 rsvd3;
|
|
u8 signature;
|
|
u8 owner;
|
|
} __packed;
|
|
|
|
struct mlx5_cmd_prot_block {
|
|
u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
|
|
u8 rsvd0[48];
|
|
__be64 next;
|
|
__be32 block_num;
|
|
u8 rsvd1;
|
|
u8 token;
|
|
u8 ctrl_sig;
|
|
u8 sig;
|
|
};
|
|
|
|
enum {
|
|
MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
|
|
};
|
|
|
|
struct mlx5_err_cqe {
|
|
u8 rsvd0[32];
|
|
__be32 srqn;
|
|
u8 rsvd1[18];
|
|
u8 vendor_err_synd;
|
|
u8 syndrome;
|
|
__be32 s_wqe_opcode_qpn;
|
|
__be16 wqe_counter;
|
|
u8 signature;
|
|
u8 op_own;
|
|
};
|
|
|
|
struct mlx5_cqe64 {
|
|
u8 outer_l3_tunneled;
|
|
u8 rsvd0;
|
|
__be16 wqe_id;
|
|
u8 lro_tcppsh_abort_dupack;
|
|
u8 lro_min_ttl;
|
|
__be16 lro_tcp_win;
|
|
__be32 lro_ack_seq_num;
|
|
__be32 rss_hash_result;
|
|
u8 rss_hash_type;
|
|
u8 ml_path;
|
|
u8 rsvd20[2];
|
|
__be16 check_sum;
|
|
__be16 slid;
|
|
__be32 flags_rqpn;
|
|
u8 hds_ip_ext;
|
|
u8 l4_l3_hdr_type;
|
|
__be16 vlan_info;
|
|
__be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
|
|
__be32 imm_inval_pkey;
|
|
u8 rsvd40[4];
|
|
__be32 byte_cnt;
|
|
__be32 timestamp_h;
|
|
__be32 timestamp_l;
|
|
__be32 sop_drop_qpn;
|
|
__be16 wqe_counter;
|
|
u8 signature;
|
|
u8 op_own;
|
|
};
|
|
|
|
struct mlx5_mini_cqe8 {
|
|
union {
|
|
__be32 rx_hash_result;
|
|
struct {
|
|
__be16 checksum;
|
|
__be16 rsvd;
|
|
};
|
|
struct {
|
|
__be16 wqe_counter;
|
|
u8 s_wqe_opcode;
|
|
u8 reserved;
|
|
} s_wqe_info;
|
|
};
|
|
__be32 byte_cnt;
|
|
};
|
|
|
|
enum {
|
|
MLX5_NO_INLINE_DATA,
|
|
MLX5_INLINE_DATA32_SEG,
|
|
MLX5_INLINE_DATA64_SEG,
|
|
MLX5_COMPRESSED,
|
|
};
|
|
|
|
enum {
|
|
MLX5_CQE_FORMAT_CSUM = 0x1,
|
|
};
|
|
|
|
#define MLX5_MINI_CQE_ARRAY_SIZE 8
|
|
|
|
static inline u8 mlx5_get_cqe_format(struct mlx5_cqe64 *cqe)
|
|
{
|
|
return (cqe->op_own >> 2) & 0x3;
|
|
}
|
|
|
|
static inline u8 get_cqe_opcode(struct mlx5_cqe64 *cqe)
|
|
{
|
|
return cqe->op_own >> 4;
|
|
}
|
|
|
|
static inline u8 get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
|
|
{
|
|
return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
|
|
}
|
|
|
|
static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
|
|
{
|
|
return (cqe->l4_l3_hdr_type >> 4) & 0x7;
|
|
}
|
|
|
|
static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe)
|
|
{
|
|
return (cqe->l4_l3_hdr_type >> 2) & 0x3;
|
|
}
|
|
|
|
static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe)
|
|
{
|
|
return cqe->outer_l3_tunneled & 0x1;
|
|
}
|
|
|
|
static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe)
|
|
{
|
|
return cqe->l4_l3_hdr_type & 0x1;
|
|
}
|
|
|
|
static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)
|
|
{
|
|
u32 hi, lo;
|
|
|
|
hi = be32_to_cpu(cqe->timestamp_h);
|
|
lo = be32_to_cpu(cqe->timestamp_l);
|
|
|
|
return (u64)lo | ((u64)hi << 32);
|
|
}
|
|
|
|
#define MLX5_MPWQE_LOG_NUM_STRIDES_BASE (9)
|
|
#define MLX5_MPWQE_LOG_STRIDE_SZ_BASE (6)
|
|
|
|
struct mpwrq_cqe_bc {
|
|
__be16 filler_consumed_strides;
|
|
__be16 byte_cnt;
|
|
};
|
|
|
|
static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe)
|
|
{
|
|
struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
|
|
|
|
return be16_to_cpu(bc->byte_cnt);
|
|
}
|
|
|
|
static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc)
|
|
{
|
|
return 0x7fff & be16_to_cpu(bc->filler_consumed_strides);
|
|
}
|
|
|
|
static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe)
|
|
{
|
|
struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
|
|
|
|
return mpwrq_get_cqe_bc_consumed_strides(bc);
|
|
}
|
|
|
|
static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe)
|
|
{
|
|
struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
|
|
|
|
return 0x8000 & be16_to_cpu(bc->filler_consumed_strides);
|
|
}
|
|
|
|
static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe)
|
|
{
|
|
return be16_to_cpu(cqe->wqe_counter);
|
|
}
|
|
|
|
enum {
|
|
CQE_L4_HDR_TYPE_NONE = 0x0,
|
|
CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
|
|
CQE_L4_HDR_TYPE_UDP = 0x2,
|
|
CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
|
|
CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
|
|
};
|
|
|
|
enum {
|
|
CQE_RSS_HTYPE_IP = 0x3 << 2,
|
|
/* cqe->rss_hash_type[3:2] - IP destination selected for hash
|
|
* (00 = none, 01 = IPv4, 10 = IPv6, 11 = Reserved)
|
|
*/
|
|
CQE_RSS_HTYPE_L4 = 0x3 << 6,
|
|
/* cqe->rss_hash_type[7:6] - L4 destination selected for hash
|
|
* (00 = none, 01 = TCP. 10 = UDP, 11 = IPSEC.SPI
|
|
*/
|
|
};
|
|
|
|
enum {
|
|
MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
|
|
MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
|
|
MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
|
|
};
|
|
|
|
enum {
|
|
CQE_L2_OK = 1 << 0,
|
|
CQE_L3_OK = 1 << 1,
|
|
CQE_L4_OK = 1 << 2,
|
|
};
|
|
|
|
struct mlx5_sig_err_cqe {
|
|
u8 rsvd0[16];
|
|
__be32 expected_trans_sig;
|
|
__be32 actual_trans_sig;
|
|
__be32 expected_reftag;
|
|
__be32 actual_reftag;
|
|
__be16 syndrome;
|
|
u8 rsvd22[2];
|
|
__be32 mkey;
|
|
__be64 err_offset;
|
|
u8 rsvd30[8];
|
|
__be32 qpn;
|
|
u8 rsvd38[2];
|
|
u8 signature;
|
|
u8 op_own;
|
|
};
|
|
|
|
struct mlx5_wqe_srq_next_seg {
|
|
u8 rsvd0[2];
|
|
__be16 next_wqe_index;
|
|
u8 signature;
|
|
u8 rsvd1[11];
|
|
};
|
|
|
|
union mlx5_ext_cqe {
|
|
struct ib_grh grh;
|
|
u8 inl[64];
|
|
};
|
|
|
|
struct mlx5_cqe128 {
|
|
union mlx5_ext_cqe inl_grh;
|
|
struct mlx5_cqe64 cqe64;
|
|
};
|
|
|
|
enum {
|
|
MLX5_MKEY_STATUS_FREE = 1 << 6,
|
|
};
|
|
|
|
enum {
|
|
MLX5_MKEY_REMOTE_INVAL = 1 << 24,
|
|
MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
|
|
MLX5_MKEY_BSF_EN = 1 << 30,
|
|
MLX5_MKEY_LEN64 = 1 << 31,
|
|
};
|
|
|
|
struct mlx5_mkey_seg {
|
|
/* This is a two bit field occupying bits 31-30.
|
|
* bit 31 is always 0,
|
|
* bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
|
|
*/
|
|
u8 status;
|
|
u8 pcie_control;
|
|
u8 flags;
|
|
u8 version;
|
|
__be32 qpn_mkey7_0;
|
|
u8 rsvd1[4];
|
|
__be32 flags_pd;
|
|
__be64 start_addr;
|
|
__be64 len;
|
|
__be32 bsfs_octo_size;
|
|
u8 rsvd2[16];
|
|
__be32 xlt_oct_size;
|
|
u8 rsvd3[3];
|
|
u8 log2_page_size;
|
|
u8 rsvd4[4];
|
|
};
|
|
|
|
#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
|
|
|
|
enum {
|
|
MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
|
|
};
|
|
|
|
enum {
|
|
VPORT_STATE_DOWN = 0x0,
|
|
VPORT_STATE_UP = 0x1,
|
|
};
|
|
|
|
enum {
|
|
MLX5_VPORT_ADMIN_STATE_DOWN = 0x0,
|
|
MLX5_VPORT_ADMIN_STATE_UP = 0x1,
|
|
MLX5_VPORT_ADMIN_STATE_AUTO = 0x2,
|
|
};
|
|
|
|
enum {
|
|
MLX5_L3_PROT_TYPE_IPV4 = 0,
|
|
MLX5_L3_PROT_TYPE_IPV6 = 1,
|
|
};
|
|
|
|
enum {
|
|
MLX5_L4_PROT_TYPE_TCP = 0,
|
|
MLX5_L4_PROT_TYPE_UDP = 1,
|
|
};
|
|
|
|
enum {
|
|
MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
|
|
MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
|
|
MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
|
|
MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
|
|
MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
|
|
};
|
|
|
|
enum {
|
|
MLX5_MATCH_OUTER_HEADERS = 1 << 0,
|
|
MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
|
|
MLX5_MATCH_INNER_HEADERS = 1 << 2,
|
|
MLX5_MATCH_MISC_PARAMETERS_2 = 1 << 3,
|
|
MLX5_MATCH_MISC_PARAMETERS_3 = 1 << 4,
|
|
};
|
|
|
|
enum {
|
|
MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
|
|
MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
|
|
};
|
|
|
|
enum {
|
|
MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
|
|
MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
|
|
MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
|
|
};
|
|
|
|
enum mlx5_list_type {
|
|
MLX5_NVPRT_LIST_TYPE_UC = 0x0,
|
|
MLX5_NVPRT_LIST_TYPE_MC = 0x1,
|
|
MLX5_NVPRT_LIST_TYPE_VLAN = 0x2,
|
|
};
|
|
|
|
enum {
|
|
MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
|
|
MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
|
|
};
|
|
|
|
enum mlx5_wol_mode {
|
|
MLX5_WOL_DISABLE = 0,
|
|
MLX5_WOL_SECURED_MAGIC = 1 << 1,
|
|
MLX5_WOL_MAGIC = 1 << 2,
|
|
MLX5_WOL_ARP = 1 << 3,
|
|
MLX5_WOL_BROADCAST = 1 << 4,
|
|
MLX5_WOL_MULTICAST = 1 << 5,
|
|
MLX5_WOL_UNICAST = 1 << 6,
|
|
MLX5_WOL_PHY_ACTIVITY = 1 << 7,
|
|
};
|
|
|
|
enum mlx5_mpls_supported_fields {
|
|
MLX5_FIELD_SUPPORT_MPLS_LABEL = 1 << 0,
|
|
MLX5_FIELD_SUPPORT_MPLS_EXP = 1 << 1,
|
|
MLX5_FIELD_SUPPORT_MPLS_S_BOS = 1 << 2,
|
|
MLX5_FIELD_SUPPORT_MPLS_TTL = 1 << 3
|
|
};
|
|
|
|
enum mlx5_flex_parser_protos {
|
|
MLX5_FLEX_PROTO_GENEVE = 1 << 3,
|
|
MLX5_FLEX_PROTO_CW_MPLS_GRE = 1 << 4,
|
|
MLX5_FLEX_PROTO_CW_MPLS_UDP = 1 << 5,
|
|
};
|
|
|
|
/* MLX5 DEV CAPs */
|
|
|
|
/* TODO: EAT.ME */
|
|
enum mlx5_cap_mode {
|
|
HCA_CAP_OPMOD_GET_MAX = 0,
|
|
HCA_CAP_OPMOD_GET_CUR = 1,
|
|
};
|
|
|
|
enum mlx5_cap_type {
|
|
MLX5_CAP_GENERAL = 0,
|
|
MLX5_CAP_ETHERNET_OFFLOADS,
|
|
MLX5_CAP_ODP,
|
|
MLX5_CAP_ATOMIC,
|
|
MLX5_CAP_ROCE,
|
|
MLX5_CAP_IPOIB_OFFLOADS,
|
|
MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
|
|
MLX5_CAP_FLOW_TABLE,
|
|
MLX5_CAP_ESWITCH_FLOW_TABLE,
|
|
MLX5_CAP_ESWITCH,
|
|
MLX5_CAP_RESERVED,
|
|
MLX5_CAP_VECTOR_CALC,
|
|
MLX5_CAP_QOS,
|
|
MLX5_CAP_DEBUG,
|
|
MLX5_CAP_RESERVED_14,
|
|
MLX5_CAP_DEV_MEM,
|
|
MLX5_CAP_RESERVED_16,
|
|
MLX5_CAP_TLS,
|
|
MLX5_CAP_DEV_EVENT = 0x14,
|
|
/* NUM OF CAP Types */
|
|
MLX5_CAP_NUM
|
|
};
|
|
|
|
enum mlx5_pcam_reg_groups {
|
|
MLX5_PCAM_REGS_5000_TO_507F = 0x0,
|
|
};
|
|
|
|
enum mlx5_pcam_feature_groups {
|
|
MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0,
|
|
};
|
|
|
|
enum mlx5_mcam_reg_groups {
|
|
MLX5_MCAM_REGS_FIRST_128 = 0x0,
|
|
};
|
|
|
|
enum mlx5_mcam_feature_groups {
|
|
MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0,
|
|
};
|
|
|
|
enum mlx5_qcam_reg_groups {
|
|
MLX5_QCAM_REGS_FIRST_128 = 0x0,
|
|
};
|
|
|
|
enum mlx5_qcam_feature_groups {
|
|
MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0,
|
|
};
|
|
|
|
/* GET Dev Caps macros */
|
|
#define MLX5_CAP_GEN(mdev, cap) \
|
|
MLX5_GET(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)
|
|
|
|
#define MLX5_CAP_GEN_64(mdev, cap) \
|
|
MLX5_GET64(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)
|
|
|
|
#define MLX5_CAP_GEN_MAX(mdev, cap) \
|
|
MLX5_GET(cmd_hca_cap, mdev->caps.hca_max[MLX5_CAP_GENERAL], cap)
|
|
|
|
#define MLX5_CAP_ETH(mdev, cap) \
|
|
MLX5_GET(per_protocol_networking_offload_caps,\
|
|
mdev->caps.hca_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
|
|
|
|
#define MLX5_CAP_ETH_MAX(mdev, cap) \
|
|
MLX5_GET(per_protocol_networking_offload_caps,\
|
|
mdev->caps.hca_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
|
|
|
|
#define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \
|
|
MLX5_GET(per_protocol_networking_offload_caps,\
|
|
mdev->caps.hca_cur[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS], cap)
|
|
|
|
#define MLX5_CAP_ROCE(mdev, cap) \
|
|
MLX5_GET(roce_cap, mdev->caps.hca_cur[MLX5_CAP_ROCE], cap)
|
|
|
|
#define MLX5_CAP_ROCE_MAX(mdev, cap) \
|
|
MLX5_GET(roce_cap, mdev->caps.hca_max[MLX5_CAP_ROCE], cap)
|
|
|
|
#define MLX5_CAP_ATOMIC(mdev, cap) \
|
|
MLX5_GET(atomic_caps, mdev->caps.hca_cur[MLX5_CAP_ATOMIC], cap)
|
|
|
|
#define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
|
|
MLX5_GET(atomic_caps, mdev->caps.hca_max[MLX5_CAP_ATOMIC], cap)
|
|
|
|
#define MLX5_CAP_FLOWTABLE(mdev, cap) \
|
|
MLX5_GET(flow_table_nic_cap, mdev->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap)
|
|
|
|
#define MLX5_CAP64_FLOWTABLE(mdev, cap) \
|
|
MLX5_GET64(flow_table_nic_cap, (mdev)->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap)
|
|
|
|
#define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
|
|
MLX5_GET(flow_table_nic_cap, mdev->caps.hca_max[MLX5_CAP_FLOW_TABLE], cap)
|
|
|
|
#define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \
|
|
MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
|
|
|
|
#define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \
|
|
MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
|
|
|
|
#define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \
|
|
MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit.cap)
|
|
|
|
#define MLX5_CAP_FLOWTABLE_NIC_TX_MAX(mdev, cap) \
|
|
MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit.cap)
|
|
|
|
#define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \
|
|
MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
|
|
|
|
#define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \
|
|
MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap)
|
|
|
|
#define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \
|
|
MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
|
|
|
|
#define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \
|
|
MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap)
|
|
|
|
#define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \
|
|
MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_rdma.cap)
|
|
|
|
#define MLX5_CAP_FLOWTABLE_RDMA_RX_MAX(mdev, cap) \
|
|
MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_rdma.cap)
|
|
|
|
#define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
|
|
MLX5_GET(flow_table_eswitch_cap, \
|
|
mdev->caps.hca_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
|
|
|
|
#define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
|
|
MLX5_GET(flow_table_eswitch_cap, \
|
|
mdev->caps.hca_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
|
|
|
|
#define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
|
|
MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
|
|
|
|
#define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
|
|
MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
|
|
|
|
#define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
|
|
MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
|
|
|
|
#define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \
|
|
MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
|
|
|
|
#define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
|
|
MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
|
|
|
|
#define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \
|
|
MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
|
|
|
|
#define MLX5_CAP_ESW(mdev, cap) \
|
|
MLX5_GET(e_switch_cap, \
|
|
mdev->caps.hca_cur[MLX5_CAP_ESWITCH], cap)
|
|
|
|
#define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \
|
|
MLX5_GET64(flow_table_eswitch_cap, \
|
|
(mdev)->caps.hca_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
|
|
|
|
#define MLX5_CAP_ESW_MAX(mdev, cap) \
|
|
MLX5_GET(e_switch_cap, \
|
|
mdev->caps.hca_max[MLX5_CAP_ESWITCH], cap)
|
|
|
|
#define MLX5_CAP_ODP(mdev, cap)\
|
|
MLX5_GET(odp_cap, mdev->caps.hca_cur[MLX5_CAP_ODP], cap)
|
|
|
|
#define MLX5_CAP_ODP_MAX(mdev, cap)\
|
|
MLX5_GET(odp_cap, mdev->caps.hca_max[MLX5_CAP_ODP], cap)
|
|
|
|
#define MLX5_CAP_VECTOR_CALC(mdev, cap) \
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MLX5_GET(vector_calc_cap, \
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mdev->caps.hca_cur[MLX5_CAP_VECTOR_CALC], cap)
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#define MLX5_CAP_QOS(mdev, cap)\
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MLX5_GET(qos_cap, mdev->caps.hca_cur[MLX5_CAP_QOS], cap)
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#define MLX5_CAP_DEBUG(mdev, cap)\
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MLX5_GET(debug_cap, mdev->caps.hca_cur[MLX5_CAP_DEBUG], cap)
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#define MLX5_CAP_PCAM_FEATURE(mdev, fld) \
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MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
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#define MLX5_CAP_PCAM_REG(mdev, reg) \
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MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg)
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#define MLX5_CAP_MCAM_REG(mdev, reg) \
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MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg)
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#define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
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MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
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#define MLX5_CAP_QCAM_REG(mdev, fld) \
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MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)
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#define MLX5_CAP_QCAM_FEATURE(mdev, fld) \
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MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld)
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#define MLX5_CAP_FPGA(mdev, cap) \
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MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
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#define MLX5_CAP64_FPGA(mdev, cap) \
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MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
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#define MLX5_CAP_DEV_MEM(mdev, cap)\
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MLX5_GET(device_mem_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_MEM], cap)
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#define MLX5_CAP64_DEV_MEM(mdev, cap)\
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MLX5_GET64(device_mem_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_MEM], cap)
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#define MLX5_CAP_TLS(mdev, cap) \
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MLX5_GET(tls_cap, (mdev)->caps.hca_cur[MLX5_CAP_TLS], cap)
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#define MLX5_CAP_DEV_EVENT(mdev, cap)\
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MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca_cur[MLX5_CAP_DEV_EVENT], cap)
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enum {
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MLX5_CMD_STAT_OK = 0x0,
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MLX5_CMD_STAT_INT_ERR = 0x1,
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MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
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MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
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MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
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MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
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MLX5_CMD_STAT_RES_BUSY = 0x6,
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MLX5_CMD_STAT_LIM_ERR = 0x8,
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MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
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MLX5_CMD_STAT_IX_ERR = 0xa,
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MLX5_CMD_STAT_NO_RES_ERR = 0xf,
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MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
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MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
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MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
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MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
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MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
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};
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enum {
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MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
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MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
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MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
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MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
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MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
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MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
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MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
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MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12,
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MLX5_PER_TRAFFIC_CLASS_CONGESTION_GROUP = 0x13,
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MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16,
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MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
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};
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enum {
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MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0,
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};
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static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
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{
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if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
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return 0;
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return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
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}
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#define MLX5_BY_PASS_NUM_REGULAR_PRIOS 16
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#define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 16
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#define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
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#define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
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MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
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MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
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#endif /* MLX5_DEVICE_H */
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