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![Linus Torvalds](/assets/img/avatar_default.png)
MTD core changes: - New Hyperbus framework - New _is_locked (concat) implementation - Various cleanups NAND core changes: - use longest matching pattern in ->exec_op() default parser - export NAND operation tracer - add flag to indicate panic_write in MTD - use kzalloc() instead of kmalloc() and memset() Raw NAND controller drivers changes: - brcmnand: * fix BCH ECC layout for large page NAND parts * fallback to detected ecc-strength, ecc-step-size * when oops in progress use pio and interrupt polling * code refactor code to introduce helper functions * add support for v7.3 controller - FSMC: * use nand_op_trace for operation tracing - GPMI: * move all driver code into single file * various cleanups (including dmaengine changes) * use runtime PM to manage clocks * implement exec_op - MTK: * correct low level time calculation of r/w cycle * improve data sampling timing for read cycle * add validity check for CE# pin setting * fix wrongly assigned OOB buffer pointer issue * re-license MTK NAND driver as Dual MIT/GPL - STM32: * manage the get_irq error case * increase DMA completion timeouts Raw NAND chips drivers changes: - Macronix: add read-retry support Onenand driver changes: - add support for 8Gb datasize chips - avoid fall-through warnings SPI-NAND changes: - define macros for page-read ops with three-byte addresses - add support for two-byte device IDs and then for GigaDevice GD5F1GQ4UFxxG - add initial support for Paragon PN26G0xA - handle the case where the last page read has bitflips SPI-NOR core changes: - add support for the mt25ql02g and w25q16jv flashes - print error in case of jedec read id fails - is25lp256: add post BFPT fix to correct the addr_width SPI NOR controller drivers changes: - intel-spi: Add support for Intel Elkhart Lake SPI serial flash - smt32: remove the driver as the driver was replaced by spi-stm32-qspi.c - cadence-quadspi: add reset control -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEE9HuaYnbmDhq/XIDIJWrqGEe9VoQFAl0qLr4ACgkQJWrqGEe9 VoQVCwf/ZCG5CldS3cs6B68kMJoZ/rJyJxBnxtIhffda2vw1KG/12o6XaDO9xA/R EwYrOTzlYZxzCZsNvWyHepG3Kj3d38CJ52ZqhavjpihwMlKKOgW/K39xuKWCrfxS sVMLz/UdrcsQfcPGAy7DSyqhzRAtupNxngCdEkIIMGFZWsv4uZfOFEGMrzUJ5RYN /okIyUE7Iz0dRq1/KXSl365V1MS8QP2eHFuHrUd38+kJ8TJnQjXX3Bmdul4aNTx+ HIIpykovoAn5BZ0YA4lJL90zVoDOWysARwHIAMDvJa8zS0wDTU16Tj2M6AQK+a4x hbIOOkeX0hTKpJvy7/khli5y1bn2mw== =L+tV -----END PGP SIGNATURE----- Merge tag 'mtd/for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux Pull MTD updates from Miquel Raynal: "This contains the following changes for MTD: MTD core changes: - New Hyperbus framework - New _is_locked (concat) implementation - Various cleanups NAND core changes: - use longest matching pattern in ->exec_op() default parser - export NAND operation tracer - add flag to indicate panic_write in MTD - use kzalloc() instead of kmalloc() and memset() Raw NAND controller drivers changes: - brcmnand: - fix BCH ECC layout for large page NAND parts - fallback to detected ecc-strength, ecc-step-size - when oops in progress use pio and interrupt polling - code refactor code to introduce helper functions - add support for v7.3 controller - FSMC: - use nand_op_trace for operation tracing - GPMI: - move all driver code into single file - various cleanups (including dmaengine changes) - use runtime PM to manage clocks - implement exec_op - MTK: - correct low level time calculation of r/w cycle - improve data sampling timing for read cycle - add validity check for CE# pin setting - fix wrongly assigned OOB buffer pointer issue - re-license MTK NAND driver as Dual MIT/GPL - STM32: - manage the get_irq error case - increase DMA completion timeouts Raw NAND chips drivers changes: - Macronix: add read-retry support Onenand driver changes: - add support for 8Gb datasize chips - avoid fall-through warnings SPI-NAND changes: - define macros for page-read ops with three-byte addresses - add support for two-byte device IDs and then for GigaDevice GD5F1GQ4UFxxG - add initial support for Paragon PN26G0xA - handle the case where the last page read has bitflips SPI-NOR core changes: - add support for the mt25ql02g and w25q16jv flashes - print error in case of jedec read id fails - is25lp256: add post BFPT fix to correct the addr_width SPI NOR controller drivers changes: - intel-spi: Add support for Intel Elkhart Lake SPI serial flash - smt32: remove the driver as the driver was replaced by spi-stm32-qspi.c - cadence-quadspi: add reset control" * tag 'mtd/for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (60 commits) mtd: concat: implement _is_locked mtd operation mtd: concat: refactor concat_lock/concat_unlock mtd: abi: do not use C++ style comments in uapi header mtd: afs: remove unneeded NULL check mtd: rawnand: stm32_fmc2: increase DMA completion timeouts mtd: rawnand: Use kzalloc() instead of kmalloc() and memset() mtd: hyperbus: Add driver for TI's HyperBus memory controller mtd: spinand: read returns badly if the last page has bitflips mtd: spinand: Add initial support for Paragon PN26G0xA mtd: rawnand: mtk: Re-license MTK NAND driver as Dual MIT/GPL mtd: rawnand: gpmi: remove double assignment to block_size dt-bindings: mtd: brcmnand: Add brcmnand, brcmnand-v7.3 support mtd: rawnand: brcmnand: Add support for v7.3 controller mtd: rawnand: brcmnand: Refactored code to introduce helper functions mtd: rawnand: brcmnand: When oops in progress use pio and interrupt polling mtd: Add flag to indicate panic_write mtd: rawnand: Add Macronix NAND read retry support mtd: onenand: Avoid fall-through warnings mtd: spinand: Add support for GigaDevice GD5F1GQ4UFxxG mtd: spinand: Add support for two-byte device IDs ...
221 lines
7 KiB
C
221 lines
7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* linux/include/linux/mtd/onenand_regs.h
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*
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* OneNAND Register header file
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*
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* Copyright (C) 2005-2007 Samsung Electronics
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* Kyungmin Park <kyungmin.park@samsung.com>
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*/
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#ifndef __ONENAND_REG_H
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#define __ONENAND_REG_H
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/* Memory Address Map Translation (Word order) */
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#define ONENAND_MEMORY_MAP(x) ((x) << 1)
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/*
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* External BufferRAM area
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*/
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#define ONENAND_BOOTRAM ONENAND_MEMORY_MAP(0x0000)
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#define ONENAND_DATARAM ONENAND_MEMORY_MAP(0x0200)
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#define ONENAND_SPARERAM ONENAND_MEMORY_MAP(0x8010)
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/*
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* OneNAND Registers
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*/
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#define ONENAND_REG_MANUFACTURER_ID ONENAND_MEMORY_MAP(0xF000)
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#define ONENAND_REG_DEVICE_ID ONENAND_MEMORY_MAP(0xF001)
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#define ONENAND_REG_VERSION_ID ONENAND_MEMORY_MAP(0xF002)
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#define ONENAND_REG_DATA_BUFFER_SIZE ONENAND_MEMORY_MAP(0xF003)
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#define ONENAND_REG_BOOT_BUFFER_SIZE ONENAND_MEMORY_MAP(0xF004)
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#define ONENAND_REG_NUM_BUFFERS ONENAND_MEMORY_MAP(0xF005)
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#define ONENAND_REG_TECHNOLOGY ONENAND_MEMORY_MAP(0xF006)
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#define ONENAND_REG_START_ADDRESS1 ONENAND_MEMORY_MAP(0xF100)
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#define ONENAND_REG_START_ADDRESS2 ONENAND_MEMORY_MAP(0xF101)
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#define ONENAND_REG_START_ADDRESS3 ONENAND_MEMORY_MAP(0xF102)
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#define ONENAND_REG_START_ADDRESS4 ONENAND_MEMORY_MAP(0xF103)
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#define ONENAND_REG_START_ADDRESS5 ONENAND_MEMORY_MAP(0xF104)
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#define ONENAND_REG_START_ADDRESS6 ONENAND_MEMORY_MAP(0xF105)
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#define ONENAND_REG_START_ADDRESS7 ONENAND_MEMORY_MAP(0xF106)
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#define ONENAND_REG_START_ADDRESS8 ONENAND_MEMORY_MAP(0xF107)
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#define ONENAND_REG_START_BUFFER ONENAND_MEMORY_MAP(0xF200)
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#define ONENAND_REG_COMMAND ONENAND_MEMORY_MAP(0xF220)
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#define ONENAND_REG_SYS_CFG1 ONENAND_MEMORY_MAP(0xF221)
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#define ONENAND_REG_SYS_CFG2 ONENAND_MEMORY_MAP(0xF222)
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#define ONENAND_REG_CTRL_STATUS ONENAND_MEMORY_MAP(0xF240)
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#define ONENAND_REG_INTERRUPT ONENAND_MEMORY_MAP(0xF241)
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#define ONENAND_REG_START_BLOCK_ADDRESS ONENAND_MEMORY_MAP(0xF24C)
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#define ONENAND_REG_END_BLOCK_ADDRESS ONENAND_MEMORY_MAP(0xF24D)
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#define ONENAND_REG_WP_STATUS ONENAND_MEMORY_MAP(0xF24E)
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#define ONENAND_REG_ECC_STATUS ONENAND_MEMORY_MAP(0xFF00)
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#define ONENAND_REG_ECC_M0 ONENAND_MEMORY_MAP(0xFF01)
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#define ONENAND_REG_ECC_S0 ONENAND_MEMORY_MAP(0xFF02)
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#define ONENAND_REG_ECC_M1 ONENAND_MEMORY_MAP(0xFF03)
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#define ONENAND_REG_ECC_S1 ONENAND_MEMORY_MAP(0xFF04)
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#define ONENAND_REG_ECC_M2 ONENAND_MEMORY_MAP(0xFF05)
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#define ONENAND_REG_ECC_S2 ONENAND_MEMORY_MAP(0xFF06)
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#define ONENAND_REG_ECC_M3 ONENAND_MEMORY_MAP(0xFF07)
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#define ONENAND_REG_ECC_S3 ONENAND_MEMORY_MAP(0xFF08)
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/*
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* Device ID Register F001h (R)
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*/
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#define DEVICE_IS_FLEXONENAND (1 << 9)
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#define FLEXONENAND_PI_MASK (0x3ff)
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#define FLEXONENAND_PI_UNLOCK_SHIFT (14)
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#define ONENAND_DEVICE_DENSITY_MASK (0xf)
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#define ONENAND_DEVICE_DENSITY_SHIFT (4)
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#define ONENAND_DEVICE_IS_DDP (1 << 3)
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#define ONENAND_DEVICE_IS_DEMUX (1 << 2)
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#define ONENAND_DEVICE_VCC_MASK (0x3)
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#define ONENAND_DEVICE_DENSITY_512Mb (0x002)
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#define ONENAND_DEVICE_DENSITY_1Gb (0x003)
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#define ONENAND_DEVICE_DENSITY_2Gb (0x004)
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#define ONENAND_DEVICE_DENSITY_4Gb (0x005)
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#define ONENAND_DEVICE_DENSITY_8Gb (0x006)
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/*
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* Version ID Register F002h (R)
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*/
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#define ONENAND_VERSION_PROCESS_SHIFT (8)
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/*
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* Technology Register F006h (R)
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*/
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#define ONENAND_TECHNOLOGY_IS_MLC (1 << 0)
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/*
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* Start Address 1 F100h (R/W) & Start Address 2 F101h (R/W)
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*/
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#define ONENAND_DDP_SHIFT (15)
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#define ONENAND_DDP_CHIP0 (0)
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#define ONENAND_DDP_CHIP1 (1 << ONENAND_DDP_SHIFT)
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/*
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* Start Address 8 F107h (R/W)
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*/
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/* Note: It's actually 0x3f in case of SLC */
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#define ONENAND_FPA_MASK (0x7f)
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#define ONENAND_FPA_SHIFT (2)
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#define ONENAND_FSA_MASK (0x03)
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/*
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* Start Buffer Register F200h (R/W)
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*/
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#define ONENAND_BSA_MASK (0x03)
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#define ONENAND_BSA_SHIFT (8)
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#define ONENAND_BSA_BOOTRAM (0 << 2)
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#define ONENAND_BSA_DATARAM0 (2 << 2)
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#define ONENAND_BSA_DATARAM1 (3 << 2)
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/* Note: It's actually 0x03 in case of SLC */
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#define ONENAND_BSC_MASK (0x07)
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/*
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* Command Register F220h (R/W)
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*/
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#define ONENAND_CMD_READ (0x00)
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#define ONENAND_CMD_READOOB (0x13)
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#define ONENAND_CMD_PROG (0x80)
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#define ONENAND_CMD_PROGOOB (0x1A)
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#define ONENAND_CMD_2X_PROG (0x7D)
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#define ONENAND_CMD_2X_CACHE_PROG (0x7F)
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#define ONENAND_CMD_UNLOCK (0x23)
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#define ONENAND_CMD_LOCK (0x2A)
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#define ONENAND_CMD_LOCK_TIGHT (0x2C)
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#define ONENAND_CMD_UNLOCK_ALL (0x27)
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#define ONENAND_CMD_ERASE (0x94)
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#define ONENAND_CMD_MULTIBLOCK_ERASE (0x95)
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#define ONENAND_CMD_ERASE_VERIFY (0x71)
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#define ONENAND_CMD_RESET (0xF0)
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#define ONENAND_CMD_OTP_ACCESS (0x65)
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#define ONENAND_CMD_READID (0x90)
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#define FLEXONENAND_CMD_PI_UPDATE (0x05)
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#define FLEXONENAND_CMD_PI_ACCESS (0x66)
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#define FLEXONENAND_CMD_RECOVER_LSB (0x05)
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/* NOTE: Those are not *REAL* commands */
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#define ONENAND_CMD_BUFFERRAM (0x1978)
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#define FLEXONENAND_CMD_READ_PI (0x1985)
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/*
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* System Configuration 1 Register F221h (R, R/W)
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*/
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#define ONENAND_SYS_CFG1_SYNC_READ (1 << 15)
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#define ONENAND_SYS_CFG1_BRL_7 (7 << 12)
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#define ONENAND_SYS_CFG1_BRL_6 (6 << 12)
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#define ONENAND_SYS_CFG1_BRL_5 (5 << 12)
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#define ONENAND_SYS_CFG1_BRL_4 (4 << 12)
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#define ONENAND_SYS_CFG1_BRL_3 (3 << 12)
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#define ONENAND_SYS_CFG1_BRL_10 (2 << 12)
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#define ONENAND_SYS_CFG1_BRL_9 (1 << 12)
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#define ONENAND_SYS_CFG1_BRL_8 (0 << 12)
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#define ONENAND_SYS_CFG1_BRL_SHIFT (12)
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#define ONENAND_SYS_CFG1_BL_32 (4 << 9)
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#define ONENAND_SYS_CFG1_BL_16 (3 << 9)
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#define ONENAND_SYS_CFG1_BL_8 (2 << 9)
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#define ONENAND_SYS_CFG1_BL_4 (1 << 9)
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#define ONENAND_SYS_CFG1_BL_CONT (0 << 9)
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#define ONENAND_SYS_CFG1_BL_SHIFT (9)
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#define ONENAND_SYS_CFG1_NO_ECC (1 << 8)
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#define ONENAND_SYS_CFG1_RDY (1 << 7)
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#define ONENAND_SYS_CFG1_INT (1 << 6)
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#define ONENAND_SYS_CFG1_IOBE (1 << 5)
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#define ONENAND_SYS_CFG1_RDY_CONF (1 << 4)
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#define ONENAND_SYS_CFG1_VHF (1 << 3)
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#define ONENAND_SYS_CFG1_HF (1 << 2)
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#define ONENAND_SYS_CFG1_SYNC_WRITE (1 << 1)
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/*
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* Controller Status Register F240h (R)
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*/
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#define ONENAND_CTRL_ONGO (1 << 15)
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#define ONENAND_CTRL_LOCK (1 << 14)
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#define ONENAND_CTRL_LOAD (1 << 13)
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#define ONENAND_CTRL_PROGRAM (1 << 12)
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#define ONENAND_CTRL_ERASE (1 << 11)
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#define ONENAND_CTRL_ERROR (1 << 10)
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#define ONENAND_CTRL_RSTB (1 << 7)
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#define ONENAND_CTRL_OTP_L (1 << 6)
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#define ONENAND_CTRL_OTP_BL (1 << 5)
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/*
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* Interrupt Status Register F241h (R)
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*/
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#define ONENAND_INT_MASTER (1 << 15)
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#define ONENAND_INT_READ (1 << 7)
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#define ONENAND_INT_WRITE (1 << 6)
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#define ONENAND_INT_ERASE (1 << 5)
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#define ONENAND_INT_RESET (1 << 4)
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#define ONENAND_INT_CLEAR (0 << 0)
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/*
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* NAND Flash Write Protection Status Register F24Eh (R)
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*/
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#define ONENAND_WP_US (1 << 2)
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#define ONENAND_WP_LS (1 << 1)
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#define ONENAND_WP_LTS (1 << 0)
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/*
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* ECC Status Reigser FF00h (R)
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*/
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#define ONENAND_ECC_1BIT (1 << 0)
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#define ONENAND_ECC_1BIT_ALL (0x5555)
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#define ONENAND_ECC_2BIT (1 << 1)
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#define ONENAND_ECC_2BIT_ALL (0xAAAA)
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#define FLEXONENAND_UNCORRECTABLE_ERROR (0x1010)
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#define ONENAND_ECC_3BIT (1 << 2)
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#define ONENAND_ECC_4BIT (1 << 3)
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#define ONENAND_ECC_4BIT_UNCORRECTABLE (0x1010)
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/*
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* One-Time Programmable (OTP)
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*/
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#define FLEXONENAND_OTP_LOCK_OFFSET (2048)
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#define ONENAND_OTP_LOCK_OFFSET (14)
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#endif /* __ONENAND_REG_H */
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