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a9372a5fb2
Similar to MMP2, which this patch is based on. Known differencies from MMP2 are: * Two PJ4B cores instead of one PJ4 * Tauros 3 L2 cache controller instead of Tauros 2 * A GIC interrupt controller optionally used instead of the MMP one * A TWD local timer * Different USB2 PHY * A USB3 SS controller * More interrupt muxes Hard to tell what else is different, because documentation is not available. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
17 lines
440 B
Makefile
17 lines
440 B
Makefile
# SPDX-License-Identifier: GPL-2.0
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#
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# Makefile for mmp specific clk
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#
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obj-y += clk-apbc.o clk-apmu.o clk-frac.o clk-mix.o clk-gate.o clk.o
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obj-$(CONFIG_RESET_CONTROLLER) += reset.o
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obj-$(CONFIG_MACH_MMP_DT) += clk-of-pxa168.o clk-of-pxa910.o
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obj-$(CONFIG_COMMON_CLK_MMP2) += clk-of-mmp2.o
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obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
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obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o
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obj-$(CONFIG_CPU_MMP2) += clk-mmp2.o
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obj-y += clk-of-pxa1928.o
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